With the continuous increase in transistor counts on a single chip, the complexity of RTL verification has grown exponentially, and completing a full simulation flow often takes several months. In industrial practice, RTL simulation is typically divided into two stages: functional debugging and system verification. Functional debugging emphasizes fast compilation and is usually performed on multi-core CPUs, while system verification demands extremely high simulation speed and often relies on FPGA acceleration. However, the limited performance of CPU-based simulation has become a major bottleneck that restricts overall design productivity.To address this challenge, we propose RAMP, a scalable multi-core RTL simulation platform that balances fast compilation with high-throughput execution. RAMP leverages a specialized architecture and compilation strategy to accelerate both combinational logic evaluation and sequential logic synchronization. For combinational logic, it adopts a balanced DAG partitioning method together with highly efficient Boolean computation cores; for sequential logic, it employs a low-latency on-chip network (NoC) to achieve efficient state synchronization across cores. Experimental results demonstrate that RAMP achieves up to 12.9× speedup over state-of-the-art multi-core simulators.

Currently, untrusted third-party entities are increasingly involved in various stages of IC design and manufacturing, posing a significant threat to the reliability and security of SoCs due to the presence of hardware Trojans (HTs). In this paper, gate-level HT detection methods based on graph neural networks (GNNs) are established to overcome the defects of existing machine learning, which makes it difficult to characterize circuit connection relationships. We introduce harmonic centrality in the feature engineering of gate-level HT detection, which reflects the positional information of nodes and their adjacent nodes in the graph, thereby enhancing the quality of feature engineering. We use the golden section weight optimization algorithm to configure penalty weights to alleviate the problem of extreme data imbalance. In the SAED database, GraphSAGE-LSTM model obtained a TPR of 88.06% and an average F1 score of 90.95%. In the combined HT netlist of LEDA datasets, GraphSAGE-POOL model obtains a TPR of 88.50% and the best F1 score of 92.17%. In sequential HT netlist, GraphSAGE-LSTM model performs optimally, with a TPR of 98.25% and an average F1 score of 98.59%. Compared to existing detection models, the F1 score is enhanced by 8.86% and 2.48% on combined and sequential HT datasets, respectively.

The introduction of multiple transform types into the Versatile Video Coding (VVC) standard has yielded notable encoding gains but also resulted in substantial computational burdens, posing two critical challenges for hardware implementation: fast kernel selection and efficient transform computation design. Existing studies typically address these challenges in isolation, lacking a holistic solution for VVC transform coding. In this paper, we presents a groundbreaking transform accelerator that unifies transform kernel selection and multiple transform circuit within a single framework. In terms of algorithms, driven by mechanistic analysis, we propose a decision tree-based kernel selection algorithm that ensures both high decision accuracy and computational efficiency. Additionally, we design a transfer matrix-based approximation algorithm for Discrete Sine Transform Type-7 and a matrix decomposition-based improved computation for Discrete Cosine Transform Type-2, significantly reducing the computational complexity. On the hardware front, we implement a high-precision and area-efficient transform accelerator, which integrates highly pipelined kernel selection and transform computation architectures. With multiple reuse and parallelism strategies, the accelerator demonstrates substantial resource efficiency advantages. Experimental results reveal that the proposed accelerator achieves a circuit resource reduction of over 44% with a slight performance degradation, while maintaining processing capabilities up to 8K@57 fps. To the best of our knowledge, this is the first comprehensive hardware solution for VVC transform coding that jointly addresses the challenges of kernel selection and transform circuit design.

The existing hardware Trojan (HT) detection technology usually relies on the golden reference model. With the continuous improvement of circuit integration, the detection accuracy of traditional methods such as side-channel analysis has declined. Methods based on testability and switch probability analysis have shown high detection accuracy. However, these techniques have a limited detection scope and are generally ineffective at identifying HT where the Sandia controllability/observability analysis program (SCOAP) values or switch probabilities are similar to those of normal signals. Against this backdrop, this article proposes a detection method based on graph neural networks (GNNs), which can achieve HT detection at the register transfer level (RTL) without the golden reference model. First, the RTL code is transformed into a data flow graph (DFG), and node feature extraction and node label marking are carried out during the transformation process. To mitigate the impact of insufficient initial features on the GNN model performance, the node feature vector used in this article comprises 37-D node types and 6-D structural features such as the minimum distance from the primary input (PI) and primary output (PO), in-degree, and out-degree. Subsequently, several GNN models are built for node classification tasks. The best model achieves an average of 99.1% recall and 96.7% F1-score on the open-source dataset on the Trust-Hub platform. Compared to the state-of-the-art detection results at RTL, the F1-score in this article has increased by an average of 3.8%.

Presents corrections to the paper, (Corrections to “GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features”).

Data races are common concurrency bugs in multi-threaded programs and many of them can cause server failures. They are difficult to be detected or verified due to some non-deterministic interleavings. Numerous static and dynamic program analysis techniques have been proposed to detect data races. However, some of detectors may report large amount of false races and some of them may miss lots of true races. This paper proposes RaceTracker that combines static and dynamic techniques to detect data races effectively and efficiently. First, we use current static detectors to produce potential races and identify ad-hoc synchronizations. Second, we instrument code locations corresponding to potential races to try best to expose them in controlled thread interleavings. Meanwhile, we apply the hybrid dynamic detection techniques to detect races in case they are exposed. Finally, we also apply the hybrid dynamic detection techniques to prune benign and false races mainly caused by ad-hoc synchronization. In order to increase the chances to trigger real race conditions in dynamic analysis, we use some strategies to control the schedule of threads. We have implemented our tool RaceTracker in the dynamic binary instrumentation framework PIN and evaluated with nearly 100 small data race programs from google data-race-test suit and some real-world concurrent applications from SPLASH-2 and Maple. Evaluations show that RaceTracker can identify more data races effectively compared with prior pure dynamic race verifiers and detectors. Meanwhile, compared with grouping verifier, RaceTracker only executes the program twice and reduces the average runtime overhead by 64%.

Discontinuity and polymorphism of a library function create two challenges for library function identification, which is a key technique in reverse engineering. A new hybrid representation of dependence graph and control flow graph called Execution Flow Graph (EFG) is introduced to describe the semantics of binary code. Library function identification turns to be a subgraph isomorphism testing problem since the EFG of a library function instance is isomorphic to the sub-EFG of this library function. Subgraph isomorphism detection is time-consuming. Thus, we introduce a new representation called Reduced Execution Flow Graph (REFG) based on EFG to speed up the isomorphism testing. We have proved that EFGs are subgraph isomorphic as long as their corresponding REFGs are subgraph isomorphic. The high efficiency of the REFG approach in subgraph isomorphism detection comes from fewer nodes and edges in REFGs and new lossless filters for excluding the unmatched subgraphs before detection. Experimental results show that precisions of both the EFG and REFG approaches are higher than the state-of-the-art tool and the REFG approach sharply decreases the processing time of the EFG approach with consistent precision and recall.

Library functions identification is a key technique in reverse engineering. Discontinuity and polymorphism of inline and optimized library functions in binary code create a difficult challenge for library functions identification. To solve this problem, a novel approach is developed to identify library functions. First, we introduce execution dependence graphs (EDGs) to describe the behavior characteristics of binary code. Then, by finding similar EDG subgraphs in target functions, we identify both full and inline library functions. Experimental results from the prototype tool show that the proposed method is not only capable of identifying inline functions but is also more efficient and precise than the current methods for identifying full library functions.

Abstract In binary code analysis, current function identification approaches are challenged by functions without explicit call sites and handcrafted assembly without standard prologues/epilogues. We propose a new function representation called a reverse extended control flow graph (RECFG) and a RECFG‐based method for identifying functions in stripped binary code. A function has at least one return instruction (an instruction that makes the control flow leave a function). Therefore, return instructions are more reliable than the function prologues and epilogues used by traditional methods. We first build RECFGs from any values that can be interpreted as return instructions in a code range. Then, for each independent RECFG, the multiple‐decision method chooses a subgraph as the control flow graph of a function. A prototype tool is developed for evaluation on seven open source applications, 138 binaries in MASM32 code examples, and 292 binaries in Windows XP SP3. Experimental results show that the proposed method can identify functions that cannot be identified by current methods with high precision and stable recall. Copyright © 2015 John Wiley & Sons, Ltd.

Research on biological objects requires tracking hundreds of micro-objects from the microscopy video. We propose an automated tracking framework to extract trajectories of micro-objects. This framework uses a particle probability hypothesis density (PF-PHD) tracker to implement a recursive Bayesian state estimation and trajectories association. In the framework, an ellipse target model is presented to describe the micro-objects with shape parameters instead of point-like targets. Furthermore, an orientation and positional constraint model is developed to deal with the data association of crossing trajectories in multitarget tracking. Using this framework, a significantly larger number of tracks are obtained than manual tracking. The experiments on simulated image sequences of microtubule movement are performed in order to evaluate the proposed PF-PHD tracking method.

The HMM-based segmentation-free strategy for Chinese handwriting recognition has the merit that the model parameters can be trained with text line samples without annotation of character boundaries. However, the recognition performance has been limited to the general maximum likelihood estimation framework. In this paper, we investigate the discriminative training framework based on MPE/MWE criteria in the context of Chinese handwriting recognition for the first time. It optimizes a objective function that is a smooth measure of recognition error. Then EBW procedure is used to solve such criteria. Some key issues for robust MPE/MWE training are explored. We reveal that MPE/MWE requires more training samples, however, Chinese handwriting recognition poses severe data sparsity problem. We explore the sample synthesizing to help the training process. Experiments are conducted on Chinese handwriting database and the effectiveness of MPE/MWE training is manifested. In particular, at least 28% error reduction of recognition rates is observed in MPE/MWE training with 50 copies of synthetic sample when big ram is used to approximate the language model.

The current education model and practices in the Higher education sector in China have been successful in educating students for academic excellence, for producing industry-linked and practice-oriented graduates, who could quickly fit into the industrial working environment, has been a problem. There is a big gap between the theoretical knowledge learned in school and the practical knowledge and skills needed in the industry. National Pilot School of Software (NPSS) at Harbin Institute of Technology (HIT) has started to explore the way to reform the current education system since 2002. Over the nine years practices HIT-NPSS has developed a gradually industrialization education model with industryoriented curricula and some best practices. The software engineering education model which became a factual instance in education reforming for universities, and also an answer for the Excellent Engineer Plan of State Ministry of Education in China.

Driver fatigue detection based on computer vision is considered as one of the most hopeful applications of image recognition technology. The key issue is to extract and select useful features from the driver images. In this work, we use the propertie