LPAQ is a lossless data compression algorithm that uses adaptive weighting of context models to achieve a superior compression ratio, but it comes with high computational complexity. This complexity arises from the hash mapping and weight training computations in the context and mixer model update phases. These computations, which process data at the bit level, rely heavily on contextual histories, making it difficult to parallelize computations of multiple bits using simple parallel computing paradigms. Accordingly, scheduling a pipeline that support parallel processing for all LPAQ computing steps per bit is crucial to exploring the parallel potential and improving the compression speed of LPAQ. In this paper, we propose Pipe-LPAQ, a fully pipelined (non-blocking) architecture for accelerating the LPAQ compressor on FPGA. Pipe-LPAQ provides architectural support for the complex encoding computations of LPAQ with following distinctive modules: (1) A tailored hardware architecture for state computation, named GatherHash engine, which performs parallel hash operations for six context models while ensuring complex bit-level and byte-level data dependencies. (2) Four fully pipelined architectures for probability prediction computations, that implement parallel computations of StateMap, MATCH, MIX, and SSE components. When the pipeline is set up, Pipe-LPAQ can handle 1bit input data per cycle. Experimental results show that Pipe-LPAQ maintains high compression ratios while achieving throughput ranging from 12.5 MB/s to 130.1 MB/s on a Xilinx Virtex UltraScale+ XCVU9P FPGA. This represents a$38\times $speedup compared to a high-performance CPU (Intel i9 [email protected]), and$23.4\times $and$1.91\times $speedups compared to state-of-the-art (SOTA) ASIC (TSMC 90nm CMOS@400 MHz) and FPGA (Xilinx XCVU9P@85 MHz) designs, respectively.

Finite state entropy (FSE) is a crucial component of the powerful Zstandard (ZSTD) lossless compressor. However, previous hardware implementations of FSE have used a static table method, causing major performance (compression ratio) losses. Therefore, in this paper, we propose a pipelined dynamic table FSE accelerator on FPGA to mitigate the compression performance loss. We present a fully pipelined dynamic table building design, which adjusts the state table size by setting four compression levels through configurable parameters. To better adapt to the pipelined design, we improved the normalization algorithm and proposed a parallel design scheme to reduce the encoding module’s waiting time. Our accelerator implemented on a Xilinx Kintex-7 KC705 FPGA board runs at 180MHz. To our knowledge, this is the first hardware accelerator of a dynamic table FSE. Experimental results show that our accelerator achieves throughputs of 735MB/s to 982MB/s, which is 15× to 38× faster than Intel(R) Core(TM) i7-13700K CPU at 3.40 GHz. Compared to previous state-of-the-art FPGA implementation, our accelerator improves the compression ratio by 23.89% (Silesia corpus) and 28.75% (Canterbury corpus) at essentially the same throughput.

Neural Radiance Fields (NeRF) have great potential applications in 3D spatial modeling, scene reconstruction, and related fields, such as AR/VR. However, the compute-intensive and memory-intensive characteristics of NeRF present significant obstacles for real-time applications. Therefore, this work presents CFSA, a CPU-FPGA synergies hardware accelerator that enhances the deployment of NeRF in resource-constrained environments. A multilayer perceptron (MLP) processor has been designed on an FPGA with 89% utilization for the multi-resolution hash encoding NeRF algorithm. Additionally, a grid occupancy and early termination computation unit has been created, which reduces computational effort by over $\mathbf{9 0 \%}$. An overall pipeline scheduling scheme for the CPU and FPGA has also been designed. The experimental data shows that the accelerator can render synthetic data at 7.1 FPS on the Xilinx VC709 board with 100 MHz. Compared to ICARUS, a specialized architecture for NeRF-based rendering, there is a $338.1 \times$ speed improvement and a $8.4 \times$ increase in energy. Compared to the GTX 1080 Ti GPU, there is a $1.3 \times$ speed improvement and a $20.2 \times$ increase in energy.

Abstract Human action recognition based on graph convolutional networks (GCNs) is one of the hotspots in computer vision. However, previous methods generally rely on handcrafted graph, which limits the effectiveness of the model in characterising the connections between indirectly connected joints. The limitation leads to weakened connections when joints are separated by long distances. To address the above issue, the authors propose a skeleton simplification method which aims to reduce the number of joints and the distance between joints by merging adjacent joints into simplified joints. Group convolutional block is devised to extract the internal features of the simplified joints. Additionally, the authors enhance the method by introducing multi‐scale modelling, which maps inputs into sequences across various levels of simplification. Combining with spatial temporal graph convolution, a multi‐scale skeleton simplification GCN for skeleton‐based action recognition (M3S‐GCN) is proposed for fusing multi‐scale skeleton sequences and modelling the connections between joints. Finally, M3S‐GCN is evaluated on five benchmarks of NTU RGB+D 60 (C‐Sub, C‐View), NTU RGB+D 120 (X‐Sub, X‐Set) and NW‐UCLA datasets. Experimental results show that the authors’ M3S‐GCN achieves state‐of‐the‐art performance with the accuracies of 93.0%, 97.0% and 91.2% on C‐Sub, C‐View and X‐Set benchmarks, which validates the effectiveness of the method.

We propose an adaptive binary implementation of the range version of Asymmetric Numeral Systems (rANS). First, as rANS encoder processes symbols in reverse order, we estimate the probabilities in forward order, store them into the encoder memory, and use them during the reverse encoding. It guarantees that both the encoder and the decoder have exactly the same probability estimation for each symbol. Second, we show how this approach can be implemented using probability estimation via Virtual Sliding Window (VSW). Finally, we demonstrate that comparing to rANS with a static model, the proposed adaptive binary rANS provides better compression performance having similar decoding complexity.

In skeletal representation, intra-frame differences between body joints, as well as inter-frame dynamics between body skeletons contain discriminative information for action recognition. Conventional methods for modeling human skeleton sequences generally depend on motion trajectory and body joint dependency information, thus lacking the ability to identify the inherent differences of human skeletons. In this paper, we propose a spatio-temporal difference descriptor based on a directional convolution architecture that enables us to learn the spatio-temporal differences and contextual dependencies between different body joints simultaneously. The overall model is built on a deep symmetric positive definite (SPD) metric learning architecture designed to learn discriminative manifold features with the well-designed non-linear mapping operation. Experiments on several action datasets show that our proposed method achieves up to 3% accuracy improvement over state-of-the-art methods.

Being a class of effective feature descriptors for action recognition, action representations based on skeleton sequences have yielded excellent recognition results. Most methods used to construct these action representations are based on the information from all the joint positions in actions. Unfortunately, some joints in the actions do not improve the accuracy of action recognition, and may even cause unnecessary inter-class errors. In this study, the authors propose a new method for action recognition by selecting active joints which are closely related to the movement of the body as the first step. Further, a skeleton is characterized as a set of its active-joint positions, and the set can be mapped to a point on pre-shape space to filter out the scale and translation variability. Then, a skeleton sequence (an action) can be regarded as points on the space. Because the timing-sequence relationship between skeletons is very valuable for action recognition, a tensor-based linear dynamical system (tLDS) is employed to model the temporal information of the action. To avoid using a finite-order sequence to estimate the infinite-order feature descriptor of a tLDS, the descriptor is mapped to a point on an infinite Grassmannian composed of the extended observability subspaces. The action is classified using sparse coding and dictionary learning (SCDL) on the infinite Grassmannian. Experimental results demonstrate that the recognition accuracies of the proposed method outperform state-of-the-art ones on four different action datasets.

LIDAR (light detection and ranging) based real‐time 3D perception is crucial for applications such as autonomous driving. However, most of the convolutional neural network (CNN) based methods are time‐consuming and computation‐intensive. These drawbacks are mainly attributed to the highly variable density of LIDAR point cloud and the complexity of their pipelines. To find a balance between speed and accuracy for 3D object detection from LIDAR, authors propose RTL3D, a computationally efficient Real‐time LIDAR‐based 3D detector. In RTL3D, an effective voxel‐wise feature representation is utilised to organise unstructured point cloud. By employing a sparse feature learning network (SFLN) on voxelised 3D data, RTL3D exploits the sparsity of point cloud and down‐samples 3D data into 2D. Basing on the generated 2D feature map, an optimised dense detection network (DDN) is applied to regress the oriented bounding box without relying on any predefined anchor boxes. The authors also introduce an incremental data augmentation approach which greatly improves the performance of RTL3D. Empirical experiments on public KITTI benchmark demonstrate that RTL3D achieves a competitive performance with state‐of‐the‐art works on 3D detection task. Owning to the simplicity of its single‐stage and anchor‐free design, RTL3D has a real‐time inference speed of 40 FPS.

An adaptive multialphabet arithmetic coding (AC) based on a generalized virtual sliding window (GVSW) is a novel multiplication-free AC scheme which can achieve better compression performance than existing implementations based on binarization and multiplication-free adaptive binary AC. In this brief, we propose an efficient hardware implementation of GVSW. We design a parallel update process of sliding windows, which can efficiently eliminate the sequentiality in the probability estimation procedure and introduce a partial unrolling for parallel execution of the renormalization procedure according to the statistical properties of an encoded data. The proposed architecture achieves an average throughput of 116.7 Mb/s for the Xilinx Kintex-7 KC705 platform.

Deep learning has been widely used in many visual recognition tasks owing to its powerful representation ability. However, online learning is a bottleneck to obstruct the application of deep learning in visual tracking. Although many algorithms have discarded the process of online learning during tracking, they demonstrate poor robustness to the online adaptation to appearance changes of the target. In this study, the authors design a tree structure specifically for online learning, which enables the appearance model to be updated smoothly. Once the target appearance has changed severely, a new branch is generated to avoid the fuzzy boundary of classification. In addition, active learning technique and artificial data are employed in the update to make the best of the limited knowledge about the interesting object during the tracking process. The proposed algorithm is evaluated on OTB2013 and VOT2017 benchmark and outperforms many state‐of‐the‐art methods.

In recent years, there has been renewed interest in developing methods for skeleton‐based human action recognition. In this study, the challenging problem of the similarity degree of skeleton‐based human postures is addressed. Human posture is described by screw motions between 3D rigid bodies, which can be seen as a relation matrix of 3D rigid bodies (RMRB3D). A linear subspace, a point of a Grassmannian manifold, is spanned by the orthonormal basis of matrix RMRB3D. A powerful way to compute the similarity degree between postures is researched to solve the geodesic distance between points on the Grassmannian manifold. Then representative postures are extracted through spectral clustering over representative postures. An action will be represented by a symbol sequence generated with a global linear eigenfunction constructed by spectral embedding. Finally, dynamic time warping and hidden Markov model (HMM) are used to classify these action sequences. The experimental evaluations of the proposed method on several challenging 3D action datasets show that the proposed approaches achieve promising results compared with other skeleton‐based human action recognition algorithms.

We propose a novel efficient multialphabet multiplication-free adaptive arithmetic coder. First, we generalize probability estimation via virtual sliding window for the multialphabet case and show that it does not require multiplications and provides a tradeoff between the probability adaptation speed and the precision of the probability estimation. Second, we show how the generalized virtual sliding window can be used to eliminate multiplications and divisions. Finally, we demonstrate that the proposed arithmetic coder provides better compression performance than existing implementations based on state-of-the-art multiplication-free binary arithmetic coders.

Human activity recognition has many valuable applications in computer vision. Unlike existing works, the challenging problem of the similarity degree of skeleton-based human postures is addressed. In this paper, the Relation Matrix of 3D Rigid Bodies (RMRB3D), which is a compact representation of postures, makes a powerful way to compute the similarity degree between postures. Then representative postures are built through Spectral Clustering (SC) on sample data and action sequences of discrete symbols will be generated according to a global linear eigenfunction constructed by Spectral Embedding (SE). Finally, action classifier can be modeled as temporal order by using Dynamic Time Warping (DTW) and Hidden Markov Model (HMM). The experimental evaluations of the proposed method on challenging 3D action datasets show that our approach achieves promising results.

In this paper, we propose a new hardware-efficient adaptive binary range coder (ABRC) and its very-large-scale integration (VLSI) architecture. To achieve this, we follow an approach that allows to reduce the bit capacity of the multiplication needed in the interval division part and shows how to avoid the need to use a loop in the renormalization part of ABRC. The probability estimation in the proposed ABRC is based on a lookup table free virtual sliding window. To obtain a higher compression performance, we propose a new adaptive window size selection algorithm. In comparison with an ABRC with a single window, the proposed system provides a faster probability adaptation at the initial encoding/decoding stage, and more accurate probability estimation for very low entropy binary sources. We show that the VLSI architecture of the proposed ABRC attains a throughput of 105.92 MSymbols/s on the FPGA platform, and consumes 18.15 mW for the dynamic part power. In comparison with the state-of-the-art MQ-coder (used in JPEG2000 standard) and the M-coder (used in H.264/Advanced Video Coding and H.265/High Efficiency Video Coding standards), the proposed ABRC architecture provides comparable throughput, reduced memory, and power consumption. Experimental results obtained for a wavelet video codec with JPEG2000-like bit-plane entropy coder show that the proposed ABRC allows to reduce the bit rate by 0.8%-8% in comparison with the MQ-coder and from 1.0%-24.2% in comparison with the M-coder.

A high-throughput memory-efficient arithmetic coder architecture for the set partitioning in hierarchical trees (SPIHT) image compression is proposed based on a simple context model in this paper. The architecture benefits from various optimizations performed at different levels of arithmetic coding from higher algorithm abstraction to lower circuits' implementations. First, the complex context model used by software is mitigated by designing a simple context model, which just uses the brother nodes' states in the coding zerotree of SPIHT to form context symbols for the arithmetic coding. The simple context model results in a regular access pattern during reading the wavelet transform coefficients, which is convenient to the hardware implementation, but at a cost of slight performance loss. Second, in order to avoid rescanning the wavelet transform coefficients, a breadth first search SPIHT without lists algorithm is used instead of SPIHT with lists algorithm. Especially, the coding bit-planes of each zero tree are processed in parallel. Third, an out-of-order execution mechanism for different types of context is proposed that can allocate the context symbol to the idle arithmetic coding core with a different order that of the input. For the balance of the input rate of the wavelet coefficients, eight arithmetic coders are replicated in the compression system. And in one arithmetic coder, there exists four cores to process different contexts. Fourth, several dedicated circuits are designed to further improve the throughput of the architecture. The common bit detection (CBD) circuit is used for unrolling the renormalization stage of the arithmetic coding. The carry look-ahead adder (CLA) and fast multiplier-divider are also employed to shorten the critical path in the architecture. Moreover, an adaptive clock switch mechanism can stop some invalid bit-planes' clock for the power saving purpose according to the input images. Experimental results demonstrate that the proposed architecture attains a throughput of 902.464 Mb/s at its maximum and achieves savings of 20.08% in power consumption over full bit-planes coding scheme based on field-programmable gate arrays (FPGAs).

A dual-symbol arithmetic coder architecture with reduced memory is presented for JPEG2000. Eight process elements are used for the prediction of probability interval A. And the use of a dedicated Probability Estimation Table decreases the internal memory greatly. Upon FPGA synthesis results, the architecture's throughput can reach 96.60M context symbols per second with an internal memory size of 1509 bits.

DWT has been the basis of image compression, such as in JPEG2000. This paper proposes a novel VLSI architecture that performs line-based DWT using a lifting scheme. The architecture consists of row processors, column processors, an intermediate buffer and a control module. The intermediate buffer is composed of FIFOs to store temporary results of horizontal filters. The control module schedules the output of wavelet coefficients to external memory with the priority from high to low. Horizontal filtering and vertical filtering are simultaneous, and all levels of DWT are processed parallel. The presented architecture finishes multi levels of 9/7 DWT in one image transmission time. Meanwhile, it decreases significantly memory used and hardware resource required. This architecture is suitable for various real-time image/video applications.

A flexible and effective adaptive acquisition collision avoidance (AACA) multiple access protocol is proposed. It integrates the concept of multichannel and random reservation with piggyback to effectively solve hidden terminal and exposed terminal problems caused by the multihop architecture. In the protocol, every node adaptively reserves an idle traffic channel by request-to-send and clear-to-send (RTS/CTS) dialogue on the common channel. After successful reservation, the packet transmission of related other nodes do not interrupt other nodes. The protocol can use any number of channels. It performs better than the single channel RTS/CTS protocol under the assumption of the same total bandwidth if the number of the channels is not too large experiments.

This paper presents a new multiple access control (MAC) protocol called adaptive acquisition multiple access with common-transmission channel assignment (AAMA-CT) and its improved one (AAMA-ICT) for wireless multihop mobile ad hoc networks. In the protocol, every node adaptively chooses a usable channel as its transmission channel in advance in multihop mobile environment and takes advantage of request-to-send (RTS) packet transmitted on a common channel to evoke its recipient to complete their communication process on their transmission channels without packet collisions. With this protocol, resource reservation is flexibly and effectively made on multiple channels by half-duplex radios without any help of powerful central controllers and wired backbone networks in an asynchronous fashion. The protocol can solve hidden and exposed terminal problems perfectly as is validated through analysis and simulation results.

Based on the idea of contention reservation and polling, a user-dependent perfect-scheduling multiple access (UPMA) protocol for supporting node mobility and multihop architecture is described. In the protocol, only the nodes have packets to send contend to use the channel and the nodes without traffic transmission are immediately deleted from the polling list, thus it improves channel utilization greatly. Moreover, a collision avoidance and resolution protocol is proposed to guarantee a node to access the channel rapidly. Finally, taking a wireless network with star topology as an example, the network performance of Internet data traffic is simulated and related conclusions are given.

This paper proposes a novel multiple access control (MAC) protocol, User-dependent Perfect-scheduling Multiple Access (UPMA) protocol, which supports joint transmission of voice and data packets. With the self-organizing algorithm, the exact number of mobile terminals (MT) in active state can be determined. Thus the transmission of MT can be perfectly scheduled by means of polling. Meanwhile, the unique frame structure of the UPMA protocol guarantees that the voice traffic is always transmitted prior to the data traffic. Furthermore, an effective collision resolution algorithm is proposed to guarantee rapid channel access for activated MT. Finally, performance of the UPMA protocol is evaluated by simulation and compared with the MPRMA protocol. Simulation results show that the UPMA protocol has better performance.

This paper presents a new multiple access control (MAC) protocol called adaptive acquisition collision avoidance multiple access with common-transmission code assignment (AACA-CT) for multihop ad hoc wireless networks. Multiple channels are employed in this scheme. One channel is used as the common channel for mobile users (or nodes) contending to reserve traffic channels by means of request-to-send and clear-to-send (RTS/CTS) dialogue. Other channels are used as traffic channels to transmit traffic packets without collision. With this protocol, resource reservation is flexibly and effectively made on multiple frequency bands, frequency-hopping (FH) codes or direct-sequence spread-spectrum (DSSS) codes by half-duplex radios without any help of powerful base stations (BS) or central controllers and wired backbone networks in an asynchronous fashion. The protocol can solve hidden and exposed terminal problems perfectly as is validated through analysis and numerical results. A comparison among the proposed protocol, IEEE 802.11 MAC protocols and the slotted ALOHA protocol shows that the proposed reservation-based approach has advantages over other protocols.