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David Hemmendinger

dblp:73/4790 · DBLP profile ↗
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5ranked-venue papers
3as first author
0since 2021 · last 2005
0000-0001-5144-1699ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%
Software engineering, system software, and programming languages
1 paper
Concurrent programming · 44% Requirements engineering and software design · 44% Programming languages and type systems · 13%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
asynchronous circuit design
0.112005
Early evaluation for performance enhancement in phased logic · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Integrated circuit design › asynchronous circuit design
phased logic
0.112005
Early evaluation for performance enhancement in phased logic · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Requirements engineering and software design
formal specification
0.011990
Specifying Ada Server Tasks with Executable Formal Grammars · IEEE Trans. Software Eng. 1990
Concurrent programming
synchronization
0.011990
Specifying Ada Server Tasks with Executable Formal Grammars · IEEE Trans. Software Eng. 1990
Programming languages and type systems › concurrent programming languages
ada tasking
0.011990
Specifying Ada Server Tasks with Executable Formal Grammars · IEEE Trans. Software Eng. 1990

Methods — techniques the papers use, named apart from their topics

delay-insensitive circuit design · 0.1prolog · 0.0formal grammar · 0.0
YearPublicationVenuePosition
2005 Computing history: interesting times
abstract
This poster describes a course on the history of computing, designed for both a computer science program and for general undergraduate education.
David Hemmendinger
ITiCSE1
2005 Early evaluation for performance enhancement in phased logic
abstract
Data-dependent completion time is a well-known advantage of self-timed circuits, one that allows them to operate at average rather than worst-case execution rates. A technique called early evaluation (EE) that extends this advantage by allowing self-timed modules to produce results before all of their inputs have arrived is described here. The technique can be applied to any combinational function and is integrated into the phased logic (PL) design methodology that accepts synchronous design entry and produces delay-insensitive self-timed circuits. We describe an algorithm that ensures that the resulting delay-insensitive circuits are safe, and develop a generalized method for inserting EE gates into any PL netlist. We give performance results for several benchmark circuits, including a five-stage pipelined CPU and a microprogrammed floating-point unit. Comparisons are made among clocked circuits, PL circuits, and PL circuits with EE. Simulation results show a clear performance benefit for PL circuits that use EE.
Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4
1995 Analyzing and verifying locally clocked circuits with the concurrency workbench
abstract
Locally Clocked Modules (LCMs) allow asynchronous communication between synchronous computational elements. The concurrency workbench models concurrent systems in the CCS process algebra. We describe the use of the concurrency workbench to specify, simulate, and verify implementations of LCMs and discuss its application to the specification of asynchronous circuits.
Garth Baulch, David Hemmendinger, Cherrice Traver
Great Lakes Symposium on VLSI2
1990 Specifying Ada Server Tasks with Executable Formal Grammars
abstract
The author shows how a class of concurrent programming problems can be specified with formal grammars. These grammars, more powerful than path expressions, translate readily into Ada server tasks using the rendezvous and select-statement, though they may also be applied to other synchronization constructs. The grammars may be used to clarify informal specifications, to compare different specifications, and to analyze the behavior of implementations of such specifications. They may also be easily converted into Prolog programs that can be executed to generate the strings of events accepted by a grammar or by the Ada task being modeled. The automated translation from Ada to such grammars, and from grammatical specifications to Ada is discussed. The former facilitates the analysis of Ada programs; the latter yields Ada code of high quality.>
David Hemmendinger
IEEE Trans. Software Eng.1
1985 Lazy Evaluation and Cancellation of Computations
David Hemmendinger
ICPP1