3D Network-on-Chip (NoC) technology has emerged as a compelling solution in modern System-on-Chip (SoC) designs. This NoC technology effectively addresses the escalating need for high-performance and energy-efficient on-chip communication in various applications, including High-Performance Computing (HPC), Graphics Processing Units (GPUs), and Multi-Processor SoCs (MPSoCs). However, the efficient mapping of applications onto 3D NoCs remains a complex challenge, necessitating the development of improved algorithms to address the issue. In this context, we present a novel neural mapping model with a reinforcement learning (RL) approach (NeurMap3D) to design application-specific 3D NoC-based IC. Additionally, we propose the NCTPAM (neural congestion-aware Through-Silicon Vias (TSVs) placement and application mapping) approach, which not only addresses application mapping but also incorporates TSVs placement and load balance across the TSVs for the specific application. In order to reduce the CPU execution time of NCTPAM algorithm, we propose incorporating a partial model parameter (θ) update mechanism. Experimental results indicate improved performance in terms of minimizing communication cost, load balancing across TSVs and energy consumption, highlighting the potential of our approach to enhance the efficiency of these synthesized network architectures.

Finding an optimal application mapping solution in a manycore processor is an NP-hard problem. Heuristic search techniques have the advantage of finding near-optimal solutions faster than other methods when mapping large-scale applications. However, the majority of the heuristic-based application mapping methods easily fall into local minima. Machine learning (ML) methods can learn heuristics from training data on their own, require minimal assistance from humans, and produce better mapping solutions. Recently, a reinforcement learning-based framework (RLF) has been proposed to generate the initial population for metaheuristics, designed using genetic algorithm (GA) and particle swarm optimization (PSO). The RLF framework does not incorporate reward information while generating mapping solutions. However, the model performance can be improved further by refining the network parameters using the reward information during predictions. To overcome this challenge, we propose an active search framework (ASF). For the first time, we propose a new intellectual property (IP)-core numbering scheme, which will assist ASF in learning the mapping rules more effectively. We demonstrate that REINFORCE with multiple samples (predictions) per data point improves model accuracy and reduces variance by constructing a baseline using these samples. With these, we propose two RL models: active search (ATSR) and active search with pretraining (ATSRP). According to experimental results, both ATSRP and ATSR models produce better mapping solutions compared to RLF and other state-of-the-art methods. The results suggest that the ATSRP model is better suited for performing application mapping onto a 2-D mesh-based manycore processor. Finally, we extend this framework to other performance metrics and 3-D mesh-based manycore processors.

Logic locking is a well known Design-for-Security(DfS) technique for Intellectual Property (IP) protection of digital Integrated Circuits(IC). However, various attacks on logic locking can extract the secret obfuscation key successfully. Although Boolean Satisfiability (SAT) attacks can break most of the logic locked circuits, inability to deobfuscate sequential circuits is the main limitation of this type of attacks. Several existing defense strategies exploit this fact to thwart SAT attack by obfuscating the scan-based Design-for-Testability (DfT) infrastructure. In the absence of scan access, Model Checking based circuit unrolling attacks also suffer from scalability issues. In this paper, we propose a particle swarm optimization (PSO) guided attack framework, which is capable of finding an approximate key that produces correct output in most of the cases. Unlike the SAT attacks, the proposed attack framework can work even in the absence of scan access. Unlike Model Checking attacks, it does not suffer from scalability issues, thus can be applied on significantly large sequential circuits. Experimental results show that the derived key can produce correct outputs in more than 99% cases, for the majority of the benchmark circuits, while for the rest of the circuits, a minimal error is observed. The proposed attack framework enables partial activation of large sequential circuits in the absence of scan access, which is not feasible using the existing attack frameworks.

Logic encryption is a popular Design-for-Security(DfS) solution that offers protection against the potential adversaries in the third-party fab labs and end-users. However, over the years, logic encryption has been a target of several attacks, especially Boolean satisfiability attacks. This paper exploits SAT attack's inability of deobfuscating sequential circuits as a defense against it. We propose several strategies capable of preventing the SAT attack by obfuscating the scan-based Design-for-Testability (DfT) infrastructure. Unlike the existing SAT-resilient schemes, the proposed techniques do not suffer from poor output corruption for wrong keys. This paper also offers various probable solutions for inserting the key-gates into the circuit that ensures protection against numerous other attacks, which exploit weak key-gate locations. Along with several gate-level obfuscation strategies, this paper also presents a Cellular Automata (CA) guided FSM obfuscation strategy to offer protection at a higher abstraction level, that is, RTL-level. For all the proposed schemes, rigorous security analysis against various attacks evaluates their strengths and limitations. Testability analysis also ensures that none of the proposed techniques hamper the basic testing properties of the ICs. We also present a CA-based FSM watermarking strategy that helps to detect potential theft of the designer's IP by any adversary.

A popular countermeasure against IP piracy relies on obfuscating the Finite State Machine (FSM), which is assumed to be the heart of a digital system. In this paper, we propose to use a special class of non-group additive cellular automata (CA) called D1 * CA, and it's counterpart D1 * CAdual to obfuscate each state-transition of an FSM. The synthesized FSM exhibits correct state-transitions only for a correct key, which is a designer's secret. The proposed easily testable key-controlled FSM synthesis scheme can thwart reverse engineering attacks, thus offers IP protection.

Logic Encryption has emerged to be a promising solution to the ever-increasing problem of IP piracy and counterfeiting. The state-of-the-art logic encryption techniques fail to offer adequate protection to the designs, equipped with Design-for-Testability (DfT) infrastructure. In this paper, we propose a new logic encryption strategy which prevents scan-chain guided circuit partitioning attack by introducing circular dependency among all the keys irrespective of their locations. Leveraging the circular dependency, the proposed method can also thwart path sensitization, logic cone based, and SAT attacks without adopting any complex key-gate placement algorithms.

Multi-processor System-on-Chip (MPSoC) based on Networks-On-Chip (NoC) as a communication paradigm becoming an industry standard in design of embedded system. Some class of embedded systems are designed for executing real-time services which are having stringent deadlines, failing to meet these deadlines may lead to catastrophic failure. NoC not only requires specialized architecture to deal with real time requirement but also problem of task mapping and flow priority assignment becomes more crucial. Real-time schedulability analysis is performed assuming worst-case to get the lower bound of schedulability for tasks and flows. The term schedulability defines the number of tasks and flows meeting the deadlines. Flow of data packets from source to destination node depends on the network topology of NoC and routing strategy at the routers. It improves on end to end schedulability by considering all possible minimal paths on place of fixed X-Y routing. It also considers deadlock avoidance in routing.

11This work is partially supported by the research project sponsored by the Synopsys Inc., USAWith the recent advancements of FPGA (Field Programmable Gate Array), circuits in AND-XOR plane gets its fair share of advantages due to the high testability feature of the AND-XOR networks and independence of the logic-gate area as well as delays on FPGA. Minimization of the product terms for such networks is an NP-hard problem. In this paper, we have proposed a Binary Particle Swarm Optimization (BPSO) based technique to solve the optimization problem accurately and accelerate the same using a Deep Neural Network. With the proposed technique, after testing it against various MCNC benchmark circuits, the results were very promising in terms of product terms, while utilizing significantly lesser CPU-time.

Rapid progress in technology scaling has introduced massive parallel computing systems with multiple cores on the integrated circuit (IC), in which a flexible and scalable packet-switched architecture, Network-on-Chip (NoC), is commonly used for communication among the cores. However, technology scaling has also increased the susceptibility to internal defects in such systems. So, manufacturing tests of such multicore systems is crucial and this is a complex and time-consuming process. Due to stress on time-to-market, test engineers focus on the reduction of testtime and perform parallel tests of cores. Due to aggressive technology scaling into the nanometer regime, power consumption is also becoming a significant burden. Moreover, power consumption during manufacturing tests is more as compared to normal operation. In addition, peak power consumption is often significantly higher than the average power values. The consumed power leads to high temperature and creates hotspots, which in turn leads to failure of good parts, resulting in yield loss. Thermal safety during testing is an utmost challenging problem in NoC-based multicore systems, including three-dimensional NoC-based (3D NoC) multicore systems due to stacking of layers. This work proposes a preemptive test scheduling technique for NoC-based multicore systems to reduce the testtime by minimizing conflicts of resource usage. The preemptive test scheduling problem has been formulated using Integer Linear Programming (ILP). In this article, authors have also presented a thermal-aware test scheduling technique to test cores in 2D as well as 3D stacked NoC-based multicore systems using a Particle Swarm Optimization (PSO) based approach. To improve the solution further, several innovative augmentation techniques have been incorporated in the basic PSO. Experimental results highlight the effectiveness of the proposed method in reducing testtime and peak temperature under the power constraints and achieve a tradeoff between testtime and peak temperature.

Logic encryption is a popular technique to safeguard an IC design from different security vulnerabilities. However, several recently proposed attacks exploit the weakness in key-gate placement schemes to extract the secret keys of an encrypted design. Security of a logic encryption strategy highly depends on the locations of the key-gates in a circuit. Most of the state-of-the-art logic encryption schemes suffer from the fact that the defence strategies against different attacks demand different locations for the placement of the key-gates. Therefore, it becomes incredibly challenging for a single solution to thwart all the state-of-the-art attacks. In this paper, we address this issue and propose a strategy which judiciously selects the locations of the key-gates to prevent different attacks and simultaneously satisfies another fundamental criterion of logic encryption, i.e., high output corruption for wrong keys.

Rapid progress in technology scaling makes transistors smaller and faster over successive generations, and consequently core count in a system gets increased. However, transistor power consumption no longer scales commensurately. Increased power density calls for better thermal safety of the multi-core systems, in which a flexible and scalable packet-switched architecture - Network-on-Chip (NoC) - is commonly used for communication among the cores. This paper proposes a strategy to increase the thermal safety of NoC-based systems by a graceful decrease in communication cost and an Integer Linear Programming (ILP) formulation to deal with the problem. To overcome huge computational overhead of ILP, another solution strategy, based on meta-heuristic technique, Particle Swarm Optimization (PSO) is also proposed. Several innovative augmentations have been introduced into the basic PSO to generate better quality solutions. A thermal-aware mapping heuristic is proposed to generate some intelligent solutions, which become a part of the initial population in the PSO. A trade-off has been established between communication cost and peak temperature of the die. Experiments on Big data and Graph analytical workloads are reported. The results obtained are better than those of many contemporary approaches, reported in the literature.

A novel Denial-of-Service attack for Networks-on-Chip, namely illegal packet request attack (IPRA), has been proposed and measures to mitigate the same have been addressed. Hardware Trojans, which cause these attacks, are conditionally triggered inside the routers at the buffer sites associated with local core, when the core is idle. These attacks contribute to the degradation of network performance and may even create deadlocks, which can raise serious concerns in time critical systems. A security unit has been proposed to detect these attacks and mitigate the consequent loss by guiding the control units of the corresponding buffers to either isolate or mask the attacked buffers in runtime. Area and power overheads of the proposed secure router are found to be a maximum of 1.69% and 0.63% respectively when compared to a baseline router in a 16×16 Mesh network. The proposed secure router can also improve the normalized execution time as well as energy consumption of benchmark applications under considered IPRAs.

Logic encryption is a popular technique to safeguard an IC design from different security vulnerabilities. However, several recently proposed attacks can extract the secret keys of an encrypted design. In this paper, we propose a new logic encryption strategy, which integrates an additional key generation unit with the design. The key generation unit takes external keys and performs a permutation of the keys to generate a highly interdependent key-set, which are applied to the inputs of the keygates. Experimentation on IWLS'05 benchmarks shows that our proposed strategy can thwart most of the existing attacks, thus enhances the security of logic encryption at the cost of reasonable design overheads.

In Network-on-Chip (NoC)-based multicore systems, task allocation and scheduling are known to be important problems, as they affect the performance of applications in terms of energy consumption and timing. Advancement of deep submicron technology has made it possible to scale the transistor feature size to the nanometer range, which has enabled multiple processing elements to be integrated onto a single chip. On the flipside, it has made the integrated entities on the chip more susceptible to different faults. Although a significant amount of work has been done in the domain of fault-tolerant mapping and scheduling, existing algorithms either precompute reconfigured mapping solutions at design time while anticipating fault(s) scenarios or adopt a hybrid approach wherein a part of the fault mitigation strategy relies on the design-time solution. The complexity of the problem rises further for real-time dynamic systems where new applications can arrive in the multicore platform at any time instant. For real-time systems, the validity of computation depends both on the correctness of results and on temporal constraint satisfaction. This article presents an improved fault-tolerant dynamic solution to the integrated problem of application mapping and scheduling for NoC-based multicore platforms. The developed algorithm provides a unified mapping and scheduling method for real-time systems focusing on meeting application deadlines and minimizing communication energy. A predictive model has been used to determine the failure-prone cores in the system for which a fault-tolerant resource allocation with task redundancy has been performed. By selectively using a task replication policy, the reliability of the application, executing on a given NoC platform, is improved. A detailed evaluation of the performance of the proposed algorithm has been conducted for both real and synthetic applications. When compared with other fault-tolerant algorithms reported in the literature, performance of the proposed algorithm shows an average reduction of 56.95% in task re-execution time overhead and an average improvement of 31% in communication energy. Further, for time-constrained tasks, deadline satisfaction has also been achieved for most of the test cases by the developed algorithm, whereas the techniques reported in the literature failed to meet deadline in about 45% test cases.

The IEEE 1687 Standard specifies an access network and a description language for embedded instruments. In this paper, we present an optimization technique to minimize the segment insertion bit (SIB) programming overhead for IEEE 1687-compliant access architectures. We first present an optimal solution based on dynamic programming for concurrent access schedules. This technique is then utilized to minimize the SIB programming overhead for more general hybrid access schedules. The proposed optimization technique is computationally efficient and it leads to significant reductions (as large as 97%) in the SIB programming overhead for hybrid access schedules.

The addition of express channels to a traditional mesh network-on-chip (NoC) has emerged as a viable solution to solve the problem of high latency. In this article, we address the problem of integrated mapping and synthesis for express channel--based mesh NoC topologies. An integer linear programming--based formulation has been presented for the mapping problem followed by a constructive heuristic for simultaneous application mapping and synthesis for an express channel--based NoC. The static and dynamic simulation results indicate that the obtained mappings lead to significant reduction in both average packet delay and network energy consumption. The obtained synthesized topologies were also found to be much more power efficient compared to conventional express channel topologies.

This brief proposes an on-line transparent test technique for detection of latent hard faults which develop in first-input first-output buffers of routers during field operation of NoC. The technique involves repeating tests periodically to prevent accumulation of faults. A prototype implementation of the proposed test algorithm has been integrated into the router-channel interface and on-line test has been performed with synthetic self-similar data traffic. The performance of the NoC after addition of the test circuit has been investigated in terms of throughput while the area overhead has been studied by synthesizing the test hardware. In addition, an on-line test technique for the routing logic has been proposed which considers utilizing the header flits of the data traffic movement in transporting the test patterns.

This paper presents a test infrastructure development and test scheduling strategy for 3D-SICs under resource (test pins and TSVs) and power constraints. Depending upon the various scheduling restrictions, two test scheduling strategies have been proposed with an objective to minimize the overall test time (TT) of the stack. A step-by-step approach deals with the individual dies separately and develops power-restricted test schedules for each die and finally decides test concurrency between the dies satisfying the resources and power limits of the stack. Particle Swarm Optimization (PSO) based meta search technique has been used to select the resource allocation and power distribution to individual dies and also their internal test schedules. Incorporation of PSO in two stages of optimization produces a notable reduction in the overall test time of the SIC. Another integrated approach uses PSO to generate power-constrained test schedule of the entire SIC in a single optimization step. Integrated approach produces better results than the step-by-step approach because of its higher flexibility with lesser restrictions. User may select any of the scheduling strategies depending upon the scheduling criteria.

Diagnosis is extremely important to ramp up the yield during the integrated circuit manufacturing process. It reduces the time to market and product cost. High-volume diagnosis has become crucial for yield learning. The backbone of any diagnosis algorithm is the test set in use. Application of test sets for high-volume testing is typically done in test data compression environment to reduce the test time and also the amount of data stored on the tester. For high-volume diagnosis, it is essential to use test sets having high diagnostic power in compression environment. In this work, a novel method has been proposed which combines test data compression and diagnostic power improvement algorithms. Selective Huffman coding is used as the basic test data compression scheme. To improve diagnostic power of a test set we make use of filling algorithms designed to increase the diagnostic ability of the test set.

In this paper we present a fault tolerant Mesh based Network-on-Chip design that helps to tolerate router faults along with core recovery mechanism. Spare links are used to provide a connection to horizontal and vertical routers pivoting the failed one. To compliment the modified topology a routing algorithm has been developed that uses minimal and non minimal paths to communicate between source and destination IP blocks. The system has been compared in terms of reliability and mean time to failure (MTTF) and with existing works. The performance evaluation in terms of throughput and latency has also been reported.

The temperature of a block (a region in the chip) depends on both heat generation (caused by power consumption) and heat dissipation among neighbors. Power aware test solutions targeting low power consumption during testing, may not produce an acceptable thermal aware solution. In this paper, a hardware based solution using an AND-OR block between the decompressor and each scan chain, has been utilized to deactivate some scan chains during loading to reduce peak temperature during testing. The proposed schemes require negligible hardware overhead and do not require any special patterns. Experimental results of our proposed approach on ISCAS'89 and ITC'99 benchmark circuits show a good reduction in peak temperature.

Diagnosis is extremely important to ramp up the yield during the integrated circuit manufacturing process. It reduces the time to market and product cost. The back bone of any diagnosis algorithm is the test set in use. In this paper, a novel method has been proposed to increase the diagnosability of a given test set. The proposed method, which takes as input a test set generated for high fault coverage, is capable of increasing the diagnostic power of the test set without affecting its fault coverage. It is able to achieve this with either no or small increase in number of patterns. The crux of the method lies in introducing test patterns having `X' bits into the test set without changing its coverage, and using a `X' bit filling algorithm to maximize its diagnostic power.

This paper presents a test architecture optimization and test scheduling strategy for TSV based 3D-Stacked ICs (SICs). A test scheduling heuristic, that can fit in both session-based and session-less test environments, has been used to select the test concurrency between the dies of the stack. The proposed method minimizes the overall test time of the stack, without violating the system level resource and TSV limits. Particle Swarm Optimization (PSO) based meta search technique has been used to select the resource allocation of individual dies and also their internal test schedules. Incorporation of PSO in two stages of optimization produces a notable reduction in the overall test time of SIC. Experimental results show that upto 51% reduction in test time can be achieved using our strategy, over the existing techniques.

Diagnosis is extremely important to ramp up the yield during the integrated circuit manufacturing process. It reduces the time to market and product cost. Limited observability due to test response compaction negatively affects the diagnosis procedure. When multiple chains, mapped to a single compactor, fail, diagnosis becomes extremely difficult. The procedure is even more complicated because when a circuit fails the flush test, not all the patterns are applied. Only a few of the patterns are applied and the observed responses are used to diagnose the faulty chains. In this paper, we have proposed an efficient masking strategy that will be very useful for diagnosis of scan chains when multiple scan chains fail. The proposed strategy uses the redundancy in fault detection by the test patterns and masks scan chains in such a way that enough information can be provided with small increase in test pattern count. A new tester architecture that will select and apply only those patterns having enough information for diagnosis has also been proposed. Diagnostic resolution and first hit index achieved by our method are very close to their ideal values, which validate the applicability of our approach.

This paper presents a fault tolerant reconfigurable Network-on-Chip (NoC) architecture using router redundancy. In case of occurrence of fault in the active router, the spare router takes its place thus the system operates normally. This scheme is topology independent, so any topology with defined routing algorithm is suitable for implementation. The system has been compared in terms of reliability, mean time to failure (MTTF) and area overhead with existing works. For a 10 × 10 mesh, it gives a 1.14 reliability gain over quad-spare mesh, 1.42 reliability gain over column-spare mesh and 21.195 reliability gain over normal mesh. The mean time to failure (MTTF) gains over column-spare, quad spare and normal mesh are 3.19, 7.51, and 33.38 respectively. We have also presented a system performance report which includes throughput and latency of the proposed design.

This paper presents a combined solution to the Through-Silicon-Via (TSV) placement and mapping of cores to routers in a three-dimensional Network-on-Chip (NoC) design. It takes care of TSV geometries and communication requirements between cores. Comparison has been carried out with the recent 3D mapping results. Both static and dynamic performance have been considered. It shows that an intelligent placement of TSVs coupled with mapping can improve the performance significantly.

This article proposes a reconfigurable Network-on-Chip (NoC) architecture based on mesh topology. It provides a local reconfiguration of cores to connect to any of the neighboring routers, depending upon the currently executing application. The area overhead for this local reconfiguration has been shown to be very small. We have also presented the strategy to map the cores of an application set onto this architecture. This has been achieved via a two-phase procedure. In the first phase, the cores of the combined application set are mapped tentatively to individual routers, minimizing the communication cost. In the second phase, for each application, positions of individual cores are finalized. A core gets attached to any neighbor of its tentative allocation. We have proposed Integer Linear Programming (ILP) formulation of both the phases. Since ILP takes large amount of CPU time, we have also formulated a Particle Swarm Optimization (PSO)-based solution for the two phases. A heuristic approach has also been developed for the reconfiguration. Comparison of communication cost, latency and network energy have been carried out for the applications, before and after reconfiguration. It shows significant improvement in performance via reconfiguration.

This brief proposes a framework to analyze multiple faults based on multiple fault simulation in a particle swarm optimization environment. Experimentation shows that up to ten faults can be diagnosed in a reasonable time. However, the scheme does not put any restriction on the number of simultaneous faults.

This paper presents a discrete particle swarm optimization (PSO)-based strategy to map applications on both 2-D and 3-D mesh-connected Networks-on-Chip. The basic PSO formulation has been augmented by: 1) running multiple PSOs and 2) deterministically generating a part of the initial population for PSO. The mapping results, in terms of the overall communication metric, have been compared with well-known techniques reported in the literature and also with exact methods built around integer linear programming (ILP). Our PSO-based results are superior to those from reported techniques. For smaller benchmarks, the results obtained are same as those corresponding to the ILP formulation, establishing the quality of the solution strategy.

Temperature during testing has become an important issue to be considered with the continuous improvement of VLSI technology. As increase in temperature during testing causes permanent or temporal damage of the chip, reduction in peak temperature of the chip becomes necessary. Also to bring uniformity in temperature distribution across the chip the thermal variance needs to be reduced. Temperature of a block depends on both heat generation caused by power consumption and heat dissipation among neighboring blocks in the circuit under test (CUT). Heat generation can be reduced by reducing transitions among test vectors. However, heat dissipation depends on thermal gradient. To reduce the peak temperature and thermal variance, the don't care bits present in test vectors can be filled in such a way that the transitions of a block and also of its neighbors get reduced. In this paper we have proposed a don't care filling technique which fills the don't care bits in the test vectors in a way such that peak temperature and thermal variance as well as the peak power and average power get reduced. Experimental results of our proposed approach on ISCAS'89 benchmark circuits show an enriched reduction in peak temperature and thermal variance as well as in peak power and average power with nominal CPU time.

Volume Diagnosis is extremely important to ramp up the yield during the IC manufacturing process. Limited observability due to test response compaction negatively affects the diagnosis procedure. Hence, in a compaction environment, it is important to implement Design For Diagnosis (DFD) methodology to restore diagnostic resolution. In this paper, a novel DFD technique which makes the faulty chains to behave as good chains during loading, has been proposed. As a result, the errors introduced in the responses, must occur during unloading of the scan chains. Diagnosis can then be performed by directly comparing the actual and expected responses without any fault simulation - leading to significant reduction in time. Results on benchmark circuits show that the average number of suspected cells for single chain failure is 1.27 (ideal value being 1) and the time taken for diagnosis is in the order of milli-seconds.

When multiple chains, mapped to the same compactor output fail, AND-gate masking logic at the compactor side can be used to aid in diagnosis. The basic idea is: if for some pattern, only one faulty chain is observed and all the other faulty chains are masked, then the corresponding compacted response will only be affected by the non-masked faulty chain. Such a test pattern will help to diagnose that chain.

This paper introduces a new metric to characterize test sets in terms of their diagnostic power. Our method uses much less space compared to the existing ones and is quite accurate. The metric can be utilized to increase the diagnosability of incompletely specified test sets via don't care filling. The X-filling approach can be integrated with test pattern generation tools to aid in better diagnostic pattern set generation.

Testing current high density memory chips using older algorithms is highly time consuming. March test of O(n) is the most widely used approach for its high fault coverage and systematic way of extending the test sequences. Size of the March test is guided by the number of fault models. Most of the March test generation algorithms reported so far, takes long time especially in case of number of operations exceeding seven. In this work, we propose a Particle Swarm Optimization (PSO) based March test generator which gives tests of high fault coverage, at a much lesser time compared to the existing approaches. Since the time to generate long March tests increases rapidly, in this work, we show that combining March tests of shorter lengths can replace the long March sequences without compromising fault coverage. Another bottleneck in memory testing is the power dissipation. The fitness function of the proposed PSO can be tuned to obtain March tests with high fault coverage, low power consumption, reduced peak power or a combination of any of these three. The experiments carried out confirm the effectiveness of our approach as it produces better results than those reported in the literature.

In this paper we present a method to identify don't care locations in a fully specified set of vectors, considering both fault propagation path and fault activation path. We exploit the identified X bits to convert the original vector to low power vector by dictionary based approach to minimize both dynamic and runtime leakage power. The dynamic power as well as the runtime leakage power depends on the activity in the circuit and hence depends on the sequence in which the test vectors are fed to it. We present an approach based on Particle Swarm Optimization (PSO) for vector reordering. Experiments on ISCAS89 benchmark circuits validate the effectiveness of our work. We achieve a maximum of 86.63% at an average of 60.89% reduction in dynamic power, a maximum of 6.87% at an average of 5.28% savings in terms of leakage power and a maximum of 66.55% at an average of 50.11% savings in terms of total power with respect to the original compacted test set generated by Tetramax ATPG tool.

Test mode power dissipation has been found to be much more than the functional power dissipation. Since dynamic power dissipation had a major contribution to the heat generated, most of the studies focused on reducing the transitions during testing. But at submicron technology, leakage current becomes significantly high. This demands a control on the leakage current as well. In this work, we propose techniques to simultaneously reduce the switching activity and keeping the leakage current under check. The overall average switching activity reduction is 70.01% and reduction in leakage power is about 6.31%, the maximum being 99.33% in switching and 9.92% in leakage.

Network-on-Chip (NoC) is a new paradigm for designing future SoCs. It supports high degree of reusability, scalability, and parallelism in communication. Here, we present Mesh-of-Tree (MoT) based deterministic routing for NoC architecture. MoT interconnection has the advantage of having small diameter as well as large bisection width. The routing algorithm ensures that the packet will always reach the destination through the shortest path and it is deadlock and livelock free.

In this paper, a greedy approach for minimizing the area of a Programmable Logic Array (PLA) using column folding of combinational component of Finite State Machines (FSMs) is presented. Also, the row re-ordering problem is addressed and a simple data structure is proposed to satisfy the constraints imposed by folding of columns. Genetic algorithm based formulation has been used for state encoding which gives minimally reduced two-level PLAs. Results obtained for several MCNC benchmark circuits show area improvement of 16.7% over NOVA[9], 53.1% over KISS[8] and 12.3% over STARF[7] on an average.

Power minimization is one of the very important issues in the testing of power constrained VLSI circuit. While existing literature emphasizes dynamic power reduction, leakage power is assuming more and more importance in the forthcoming technologies beyond 100 nm. This paper studies the effect of don't care filling of the patterns generated via automated test pattern generators, to make the patterns consume lesser power. It presents a trade-off in the dynamic and static power consumption. Judicious selection of don't cares can provide a trade-off of 17% dynamic power. For static power the trade-off is about 2.4% in the 0.18 mum technology. The effect is expected to be more prominent for technologies beyond 100 nm.

Recently, a block based adaptive decision feedback equalizer (ADFE) is presented which first uses an iterative scheme to evaluate a block of unknown decisions. FFT based block processing is then used on the received input block and the decision block to carry out the block ADFE operation. A direct floating point (FP) based realization of this scheme, however, pushes up the cost and complexity of processing hugely, as each FP operation involves several additional steps not present in its fixed point (FxP) counterpart. To overcome this problem, a block floating point (BFP) based treatment is presented in this paper for realization of the block ADFE. The proposed scheme, while maintaining FP like high dynamic range, deploys mostly FxP operations and thus reduces the processing cost and complexity substantially.

Due to higher switching activity within scan chain for scanning in/out of the stimuli/response pair, during testing average and peak power dissipation is much higher than the normal mode operation of a circuit. In our paper we propose a method of reducing dynamic power consumption in scan chain by introducing XOR gate at selected places in the traditional scan chain, there by converting the D flip-flops into T flip-flops temporarily during scan. This approach involves reordering of test vectors but not reordering of the scan cells. Our proposed method is verified with ISCAS89 benchmark circuits, which shows that upto 34% reduction in switching activity within modified scan architecture is possible.

This paper highlights the problem of test-bus power reduction in system-on-chip testing. It has been shown that while the cores are fitted with IEEE 1500 wrapper, transitions occurring within test bus and bypass registers can be comparable to those in the scan-chain. Unlike bus encoding the proposed solution does not use any extra hardware and neither affects the compression ratio, nor test application time. Experimental results on ISCAS89 benchmark circuits show up to 87% saving of transitions occurring in test bus in a Huffman coding based test data compression mechanism. A trade-off mechanism has also been shown between compression and test-bus power consumption.

This paper presents a Genetic algorithm (GA) based solution to co-optimize test scheduling and wrapper design under power constraints for core based System-On-Chips (SOCs). Core testing solutions are generated as a set of wrapper configurations, represented as rectangles with width equal to the number of TAM (Test Access Mechanism) channels and height equal to the corresponding testing time. A locally optimal best-fit heuristic based bin packing algorithm has been used to determine placement of rectangles minimizing the overall test times, whereas, GA has been utilized to generate the sequence of rectangles to be considered for placement. Experimental result on ITC’02 benchmark SOCs shows that the proposed method provides better test time results compared to the recent works reported in the literature.

Power dissipation in CMOS circuits during test time poses a crucial bottleneck for circuit performance and robustness. The power consumption due to switching activity while scan-in of test vectors and scan-out of responses is of particular concern. In this paper a methodology for scan chain modification and test vector adaptation is proposed to effectively reduce the scan test power consumption by controlling this switching activity. Proposed approach, unlike the many in published literature, does not incorporate reordering of scan cells; thus avoiding timing and routing overheads. ATPG software ATALANTA was used for test vector generation. The algorithm was verified for ISCAS’89 benchmark circuits, where it showed as much as 27.3% of reduction in switching activity during scan operations.

This paper presents a genetic algorithm (GA)-based approach for the synthesis of a finite state machine (FSM). Three aspects—state assignment, choice of polarity for the state bits and the polarities of the primary outputs—significantly affect the cost of the combinational logic synthesized for an FSM. Thus, the problems of state assignment, flip-flop polarity selection and output polarity selection have been integrated into a single genetic algorithmic formulation. The experiments performed on a large suite of benchmarks have established the fact that this tool outperforms the existing two-level state assignment algorithms. The quality of the solution obtained and the high rate of convergence have established the effectiveness of the GA in solving this difficult problem.

Pseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. Since it does not assume any fault model, the testing ensures detection of all static detectable faults in the circuit that do not require two-pattern tests. Earlier works on pseudoexhaustive testing usually generate test sets that are several orders of magnitude larger than the minimum size test set required for a specific circuit, and are mostly based on LFSRs. This paper presents a novel strategy for constructing circuit-specific pseudoexhaustive test pattern generators, based on cellular automata, that result in generating minimal pseudoexhaustive test sets for combinational circuits. Experimentation with ISCAS85 benchmarks show that as compared to the LFSRs, the cellular automata based approach often results in simpler circuitry with lesser number of shift stages and reduced test length. Moreover, the analytical technique developed here is generic in nature and thus can also be applied for constructing LFSR based pseudoexhaustive test pattern generators.

This paper presents a recursive technique for generation of pseudoexhaustive test patterns. The scheme is optimal in the sense that the first 2/sup k/ vectors cover all adjacent k-bit spaces exhaustively. It requires substantially less hardware than the existing methods and utilizes the regular, modular, and cascadable structure of local neighborhood Cellular Automata (CA), which is ideally suited for VLSI implementation. In terms of XOR gates, this approach outperforms earlier methods by 15 to 50 percent. Moreover, test effectiveness and hardware requirements have been established analytically, rather than by simple simulation and logic minimization.

This paper enumerates a new approach to the solution of classification problems based on the properties of Additive Cellular Automata. Classification problem plays a major role in various fields of computer science, such as grouping of the records in database systems, detection of faults in VLSI circuits, image processing, and so on. The state-transition graph of Non-group Cellular Automata (CA) consists of a set of disjoint trees rooted at some cyclic states of unit cycle length - thus forming a natural classifier. First a scheme of classifying the patterns distributed into only two classes has been dealt with. This has been further extended for solution of the multiclass classification problem. The Multiclass Classifier saves on an average 34% of memory as compared to the straight-forward approach storing directly the class of each pattern. A regular, modular, and cascadable hardware implementation of the classifier has been presented which is highly suitable for VLSI realization. The design has been specified in Verilog and verified for functional correctness.

This paper reports the use of a class of cellular automata for the testing and diagnosis of faults in analog circuits. The use of the scheme is explained with reference to the testing of OTA based circuits.

A novel scheme for board level fault diagnosis based on cellular automata array (CAA) is presented. In the proposed diagnosis scheme, the output responses of the chips are encoded by applying the strategy of CA-based byte error correcting code. The encoded response symbols for different test vectors are compressed to a signature. The decoding scheme of byte error correcting code is subsequently employed to detect the faulty chips on the board. The CAA-based design for the fault diagnosis strategy results in a simple and modular test structure that is well suited for VLSI implementation. The scheme can be applied for testing and diagnosis of multichip modules (MCMs) as well.

In the domain of combinational logic synthesis, logic minimization plays a vital role in determining the area and performance of the synthesized circuit. Logic minimization based on AND-OR decomposition of functions is a well studied area. However, minimization based on AND-XOR decomposition has received relatively lesser attention. Since many real-life combinational functions are XOR dominated, a logic minimizer producing efficient AND-XOR decomposition can lead to more efficient realization of such circuits. The computer-aided design tool KGPXORMIN presented in this paper is a multilevel AND-XOR minimizer which outperforms the scheme reported by Saul (1991) by 45.77% in the literal count metric. In general, most of the real-life and benchmark circuits are a combination of OR and XOR logic. In order to have area efficient realization, we need to have an efficient minimizer capable of judicious use of OR and XOR gates. An integrated tool KGPMIN has been developed which combines the AND-XOR minimizer KGPXORMIN and well-known AND-OR minimizer MISII. Depending on the measure of dominance of OR and XOR logic, it switches from one minimizer to the other during the decomposition phase. By judicious switching from one minimizer to the other, on the average, KGPMIN outperforms MISII by 64.08% in literal count and 45.16% in absolute gate area for the MCNC combinational logic benchmarks. It also outperforms KGPXORMIN by 17.46% in literal count and 34.32% in gate area. The number of levels of the circuits synthesized with KGPMIN can be found to be comparable with the figures arrived at from the application of MISII.

Specific inherent advantages of AND-XOR networks have encouraged researchers to look for efficient minimization and synthesis tools for their realization. Among several canonical representations of AND-XOR networks, the most easily testable one is the fixed polarity Consistent Generalized Reed Muller (CGRM) form. In this paper, a Genetic Algorithm (GA) formulation of the problem of finding the polarity of the variables resulting in minimum number of product terms has been proposed. The quality of the solution obtained and the high rate of convergence have established the effectiveness of the genetic algorithm in solving this particular NP-hard problem. Further, the inherent parallelism of genetic algorithm makes the proposed scheme an ideal candidate for solving the problem in a multiprocessor environment.

The design of a cellular automata (CA) based byte error correcting code analogous to an extended Reed-Solomon code has been proposed by Chowdhury et al. (1982, 1985). This code has the same restrictions on error correction as that of an extended R-S code. A new design scheme has been reported for parallel implementation of the CA based SbEC/DbED and DbEC/DbED code that is analogous to the conventional R-S code. Both the encoder and decoder of this code can be efficiently implemented with an array of CA (CAA) with high throughput. The design is ideally suited for high speed memory systems built with byte organized RAM chips. Extension of the scheme to detect/correct a larger number of byte errors has also been reported. Throughput of the decoder to handle tbyte errors (t/spl les/4) can be found to be substantially better than that of a conventional R-S decoder. The proposed decoder provides a simple, modular and cost effective design that is ideally suited for VLSI implementation.

With the help of real-time numerical simulation results, the acquisition properties of a second-order ZC/sub 1/-DPLL are investigated. Besides confirming the sensitivity of the system dynamics to the initial values of the state variables, it predicts qualitatively the maximum possible frequency acquisition range (FAR) of the system, and obtains the values of the maximum FAR for systems with different design parameters. The effect of jitter on the loop dynamics has also been considered.>

A dynamic modification algorithm of the conventional digital phase-locked loop (CDPLL) design parameters is proposed to get a modified DPLL (MDPLL) which has nearly symmetric two-sided acquisition range. With the help of extensive simulation results, it is established that in comparison to a CDPLL, the MDPLL has larger acquisition range and better FM demodulation capability. The performance degradation due to additive noise is more pronounced in the case of an MDPLL.>