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Philip E. Stanley

dblp:73/4911 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1978
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
instruction set architecture
0.011978
Address Size Independence in a 16-Bit Minicomputer · ISCA 1978
Processor architecture and microarchitecture › general-purpose processor architecture
minicomputer architecture
0.011978
Address Size Independence in a 16-Bit Minicomputer · ISCA 1978
Compilers and program optimization › compiler toolchain
assembler
0.011978
Address Size Independence in a 16-Bit Minicomputer · ISCA 1978
YearPublicationVenuePosition
1978 Address Size Independence in a 16-Bit Minicomputer
abstract
Most minicomputers do not distinguish in their architecture between addresses and other operands, with the result that operand size becomes a de facto limit on address size (and thus memory size). This has created serious problems for many architectures when attempting to build systems with large address space.It is possible, however, to make address size “invisible” to the programmer and independent of operand/word size. This is achieved by defining the architecture to segregate addresses from other operands, and to compensate for the number of storage words required to hold an address.In a system so designed, the assembly source code written by a programmer then becomes “independent” of the address size of the particular computer for which it is intended; differences in address size becoming the concern of only the assembler.The implementation of this concept in a new minicomputer architecture is described. The necessary features in the architecture are identified, and the manner in which the assembler treats addresses is described.The effects upon ease of programming of these features is considered, and the object code produced (from a single source code) for two systems with different address sizes is analyzed. It is found that the sample programs will be only 5% larger and 3% slower for a system with two-word addresses than for a system with one-word addresses.
Philip E. Stanley
ISCA1