In this paper, design and implementation of a multicarrier quadrature amplitude modulation (QAM) modulator for a wideband code division multiple access (WCDMA) base-station with a 14-bit on-chip D/A converter is described. The modulator is capable of modulating four carriers with four independent in phase (I) and quadrature (Q) data streams. The proposed modulator structure consists of an interpolation chain for data streams and four digital frequency synthesizer/modulators, which are based on a coordinate rotation digital computer (CORDIC) vector rotation algorithm. The interpolation chain consists of a root-raised cosine pulse shaping filter and three half-band filters for image filtering. The modulated carriers are combined to form a multicarrier WCDMA signal. The SINC-attenuation effect of a digital/analog (D/A) converter is canceled by an inverse-SINC predistortion filter. The multicarrier signal is converted to the analog domain with a 14-bit current steering D/A converter, which is integrated on the same silicon chip. The modulator is implemented with a 0.35-mum BiCMOS process with CMOS transistors only

In conventional base station solutions, the carriers transmitted are combined after the power amplifiers. An alternative to this is to combine the carriers in the digital domain. The major drawback of the digital carrier combining is a strongly varying envelope of the composite signal. The high PAR, sets strict requirements for the linearity of the power amplifier. High linearity requirements for the power amplifier leads to low power efficiency and therefore to high power consumption. In this paper, the possibility of reducing the PAR by clipping is investigated in two cases, GSM and EDGE.

A multicarrier Gaussian minimum shift keying (GMSK) modulator has been developed and implemented. The design contains four GMSK modulators, which generate GMSK modulated carriers at the specified center frequencies. Utilization of the redundancy in the stored waveforms reduces the size of the GMSK trajectory look-up table to less than one-quarter of the original size in the modulator. Conventionally, the power ramping and output power level controlling are performed in the analog domain. A novel digital ramp generator and output power level controller perform both the burst ramping and the dynamic power control in the digital domain. The power control is realized by scaling the ramp curve, which follows a raised cosine/sine curve. The four GMSK modulated signals are combined together in the digital domain. The digital multicarrier GMSK modulator is designed to fulfil the spectrum and phase error specifications of the GSM 900 and DCS 1800 base stations.

A multicarrier QAM modulator for the wideband code division multiple access (WCDMA) basestation has been designed. The multicarrier modulator performs pulse shaping filtering for four baseband I and Q data streams. The filtered data is interpolated in three stages each interpolating with a factor of two. The modulation of four independent carriers is performed with the numerically controlled oscillators (NCO) which are based on the CORDIC vector rotation algorithm. The multi-carrier output is formed by summation of the modulated carriers. The SINC-attenuation effect of the D/A-converter is canceled by an inverse-SINC predistortion filter. The goal of the design process was to make the performance of the modulator limited by the 14-bit D/A-converter which can be considered as the state of the art available at IF frequencies.

A basic premise for a direct digital synthesizer (DDS) with error feedback (EF) is that the output frequency being generated is low with respect to the clock frequency used. This is necessary because the transfer function of the EF has zero(s) at DC. In the proposed architecture the clock frequency need only be much greater than the bandwidth of the output signal, whereas the output frequency could be any frequency up to somewhat below the Nyquist frequency. In this novel method, the coefficients of the EF filter are tuned according to the output frequency.

This paper gives a description of a modulator for burst-by-burst carrier frequency hopping in TDMA systems. The architecture consists of a digital frequency synthesizer/modulator for a broad class of continuous phase modulations (CPMs) and a fast frequency settling RF synthesizer consisting of one phase-locked-loop (PLL). The performance of the digital frequency synthesizer/CPM modulator has been analyzed theoretically and simulated by a computer program. The analyses show that the proposed digital frequency synthesizer/CPM modulator achieves lower power consumption and spurious levels than the fast frequency hopping systems synthesizing digitally a full frequency band. In the computer simulations the effect of the digital frequency synthesizer/CPM modulator parameters on the power spectrum and the phase error is investigated.