This paper presents a resource-saving system to extract a few important features of electrocardiogram (ECG) signals. In addition, real-time classifiers are proposed as well to classify different types of arrhythmias via these features. The proposed feature extraction system is based on two delta-sigma modulators adopting 250 Hz sampling rate and three wave detection algorithms to analyze outputs of the modulators. It extracts essential details of each heartbeat, and the details are encoded into 68 bits data that is only 1.48% of the other comparable methods. To evaluate our classification, we use a novel patient-specific training protocol in conjunction with the MIT-BIH database and the recommendation of the AAMI to train the classifiers. The classifiers are random forests that are designed to recognize two major types of arrhythmias. They are supraventricular ectopic beats (SVEB) and ventricular ectopic beats (VEB). The performance of the arrhythmia classification reaches to the F1 scores of 81.05% for SVEB and 97.07% for VEB, which are also comparable to the state-of-the-art methods. The method provides a reliable and accurate approach to analyze ECG signals. Additionally, it also possesses time-efficient, low-complexity, and low-memory-usage advantages. Benefiting from these advantages, the method can be applied to practical ECG applications, especially wearable healthcare devices and implanted medical devices, for wave detection and arrhythmia classification.

This paper presents a method of designing the required reference signals' phases for a group of frequency synthesizers based on the congruence modulo. The resultant adjacent synthesizers' outputs possess a constant phase difference that the synthesizers can be used to control the steering beam of an array antenna. Compared with the conventional phase shifter approach, the frequency synthesizers' output phases can be accurately controlled at different frequencies as long as their input reference signals' phases are well-controlled. Compared with the other phase control mechanism using frequency synthesizers for controlling the feeding phases to an antenna array, the proposed congruence-modulo-based method is easier to be realized and the resultant system is less complicated.

This paper presents a method for designing linear-phase square-root (SR) FIR digital filters that alleviate the effect of receiver timing uncertainty by the quadratically constrained quadratic programming. As in the previous work, we take the “roughness” of the hybrid analog/FIR-SR filter impulse response as the cost function and the filter's stopband attenuation and the system's tolerable ISI as constraints. However, instead of using the time-domain formulation in the previous work, we formulate the cost function and the constraints in the frequency domain, which turns the design problem into a quadratic one. Solving the design problem by the time-domain formulation requires a good initial guess while solving the problem by the new formulation does not. Experiments on a software defined radio platform show that the designed filter by the proposed method outperforms the prior art even though the perfect clock recovery subsystem is not realized on a modern low-cost electronic communication system.

This paper presents a wide-voltage-range, fast-transient all-digital buck converter using a high-resolution digital pulsewidth modulator (DPWM). The converter employs the multithreshold-voltage band-control technique to shorten its transient response. The DPWM uses an all-digital delay-locked loop (ADDLL) to control its cycle. The usage of ADDLL leads to the DPWM possessing a small area while maintaining high cycle resolution. Moreover, the proposed ADDLL-based cyclecontrolled DPWM can achieve synchronization between its input and output. This decreases the loop delay of the proposed converter so that the system is easy to be stabilized. The prototype chips of both the ADDLL-based cycle-controlled DPWM and the all-digital buck converter are fabricated in 0.35-μm CMOS process. Measurement results of the cyclecontrolled DPWM show that the duty cycle of its output is adjustable from 1% to 99% in a 0.78% increment per step when operating at 1 MHz. The measured transition time of the all-digital buck converter is <;3.5 μs when the load current changes from 50 to 500 mA, and vice versa.

This brief presents a fast-acquisition 11-bit all-digital delay-locked loop (ADDLL) using a novel starting-bit prediction algorithm for the successive-approximation register (SBP-SAR). It can effectively eliminate the harmonic lock and the false lock. The achievable acquisition time is within 17.5-23.5 or 17.5-32.5 clock cycles when the ADDLL works at the low or high clock rate, respectively. The digital-controlled delay line and the SBP-SAR of the ADDLL chip are synthesized using Taiwan Semiconductor Manufacturing Company's (TSMC's) 0.18-μm CMOS cell library. The proposed ADDLL can operate at a clock frequency from 60 MHz to 1.1 GHz.

The previous fast-locked all-digital phase-locked loop (ADPLL) usually suffers from large timing jitter due to the steep frequency transfer curve of its digitally controlled oscillator (DCO). This paper presents an ADPLL that possesses a coarse frequency selection function. All DCO frequency transfer curves of the ADPLL have gentle slopes. The ADPLL selects one transfer curve before acquisition. To fulfill the fast-acquisition requirement, the proposed ADPLL employs the phase-frequency-error compensation technique. In the acquisition mode, the phase-error compensator resolves the problem of phase-error accumulation. Meanwhile, the frequency-error compensator predicts a proper control code by calculating the cycle time difference between the reference clock and the derived signal fed back from the DCO. Therefore, the proposed ADPLL can compensate for the phase and the frequency errors simultaneously. The experimental results show that the proposed ADPLL possesses a fine-tuning acquisition within 5 reference clock cycles. After acquisition, the code updates in a fractional manner in the tracking mode to enhance the tracking jitter performance. The ADPLL output frequency ranges from 860 MHz to 1 GHz. The measured rms jitter is 1.31 ps at 1-GHz frequency.

This paper presents a system-level simulation technique for the delta-sigma analog-to-digital converters. The integrator in an analog delta-sigma modulator consists of an op amp and the large-signal model of an op amp is nonlinear. Therefore, the conventional linearized system-level simulation of the DSM using only the linear model is not sufficiently accurate. This work employs the Newton's method in the proposed simulation technique to solve the problem encountered in the conventional simulations. The new technique is implemented using the Mat-lab/Simulink tool. The proposed method is verified by comparing the system-level simulation results with the Hspice circuit-level simulation results.

Previous high-performance delay-locked loops (DLLs) were designed in a full-custom design flow that is labor-intensive. Most of those DLLs require tens to hundreds of clock cycles to achieve synchronization of the clock signal. This paper presents an all-digital DLL (ADDLL) with constant acquisition cycles in a cell-based design flow. The proposed ADDLL circuit can acquire the phase of a clock signal from 60-MHz frequency to 1.2-GHz frequency. In this paper, the digitally controlled delay line (DCDL) is resettable such that our constant acquisition-cycle DLL algorithm can apply. This paper realizes the DCDL using lattice delay units in a linear manner, so the delay profile of our DCDL shows good linearity. On the other hand, the proposed ADDLL algorithm can effectively eliminate the harmonic lock. The ADDLL chip is implemented using the Artisan-TSMC-0.18-μm CMOS cell library. The measured power consumption of the chip is 16.2 mW at 1.2-GHz clock frequency and at 1.8 V supply voltage. The rms jitter is 1.63 ps and the peak-to-peak jitter is 12.8 ps. Both are measured at 1.2-GHz clock frequency.

This work presents a method for designing asymmetric square-root (SR) FIR filters against the effects of jitter-induced interference at the receiver. The proposed method employs the linear programming to design the Nyquist filter coefficients for minimizing the power of the jitter-induced interference. This work takes the "roughness" of the analog/FIR-SR filter impulse response into account. We show that the error-performance of a system employing a matched SR filter pair, in the presence of receiver timing jitter, is more strongly related to the roughness of the hybrid analog/FIR-SR filter's impulse response, than it is to the eye width caused by the Nyquist pulse. The design example validates the proposition that the proposed method can lead to improved error performance of a high-order QAM communication system in the presence of receiver clock jitter.

A passive RFID tag derives its power from RF signal emitted by a RFID reader and responds its modulated backscatter signals to the reader. Because of the large propagation loss, the accessible range of a passive RFID tag is hence limited. In addition, the readability of a passive RFID tag is often influenced by multipath fading problems. In order to mitigate the problems, a multi-carrier UHF passive RFID system utilizes isolated power sources which provide additional power to passive RFID tags via a carrier frequency different with the RFID reader operating frequencies. This approach however affects reader command demodulation circuit of a passive RFID tag. This work proposes a new passive tag demodulation circuit design which is more suitable for multi-carrier RFID systems.

This paper presents a method of combining the design and the implementation of fixed-point FIR filter coefficients into one design flow. The proposed method designs the fixed-point coefficients in an expanding subexpression space. During the design process, the implementation cost is estimated as well and it is fed back to the design routine such that the algorithm can redesign the fixed-point coefficients iteratively. Design examples show that, in many cases, we can obtain better hardware-cost- effective FIR filters than the results reported by other researchers.

A method for designing square-root (SR) FIR filters that are less sensitive to receiver clock jitter is proposed. Unlike previously published methods that use only frequency domain constraints, the proposed method considers time-domain constraints as well, including the inter-symbol interference (ISI) and the opening of the eye pattern at the receiver output. Design examples show that using the time-domain constraints can result in a more robust eye opening and thus a robust ISI performance in the presence of receiver clock jitter.

In this paper, a systematic method for designing linear-phase (LP) square-root (SR) FIR filters is proposed. The proposed method employs a constrained optimization algorithm to design the coefficients of the desired FIR filter. Unlike the previously published method that used the Remez exchange algorithm, the proposed method relaxes the passband equiripple constraint imposed by the Remez exchange algorithm. Design examples show that relaxing the passband constraint can result in better stopband attenuation and inter-symbol interference performance or a shorter SR filter.

In this paper, a fuzzy system-based adaptive iterative learning controller is proposed for a class of non-Lipschitz nonlinear plants which can repeat a given task over a finite time interval. The variable initial resetting state errors at the beginning of each trial is considered. To overcome the initial errors, a time-varying boundary layer is introduced to design an error function. Based on the error function, the main structure of this controller is constructed by a fuzzy iterative learning component and a feedback stabilization component. The fuzzy system is used as an approximator to compensate for the plant unknown nonlinearity. Since the optimal parameters for a good fuzzy approximation are in general unavailable, the adaptive algorithms are derived along the iteration axis to search for suitable parameter values and then guarantee the closed-loop stability and learning convergence. It is shown that all the adjustable parameters as well as internal signals remain bounded for all iterations. There even exist initial state errors, the norm of tracking error vector will asymptotically converge to a tunable residual set as iteration goes to infinity and the learning speed can be easily improved if the learning gain is large.

In this paper, we propose a new adaptive iterative learning control (AILC) scheme for a class of parametric uncertain robotic systems with disturbances. The main feature of the proposed AILC scheme is that all the estimated parameters are updated by a new adaptive law which combines time-domain and iteration-domain adaptation. This new adaptive law is designed without using projection or deadzone mechanism and can be applied to system with non-periodic or non-repeatable disturbance. Via a rigorous technical analysis, it is shown that all adjustable parameters as well as the internal signals remain bounded in the time-domain for each iteration and the tracking error can be driven to zero in the iteration-domain. Finally, the learning performance will be demonstrated by a simulation example.