Increasing dominance of process variations in the nanometer designs are posing significant challenges for circuit design and optimization. The variations in parameters such as channel length and the gate oxide thickness impacts circuit delay and power. In this paper, we propose a new gate sizing algorithm using fuzzy mathematical programming (FMP) in which the uncertainty due to process variations is modeled using fuzzy numbers. The variations in gate delay, which is a function of gate sizes and the fan-outs of the gate, are represented using triangular fuzzy numbers with linear membership functions. The variation aware gate sizing problem is formulated as a fuzzy mathematical program to perform a delay constrained power minimization in the presence of variations. Initially, a deterministic optimization is performed by fixing the fuzzy parameters to the worst and the average case values and the results are used to convert the fuzzy optimization problem into a crisp non-linear problem which is then solved using a non-linear optimization solver. The above model with delay and power as constraints, maximizes the robustness, i.e., the variation resistance of the circuit and thus the yield. The proposed approach was tested on ISCAS '85 benchmarks and the results were validated for timing yield using monte-carlo simulations. The fuzzy approach yields significantly better results compared to stochastic programming based gate sizing approach with a comparable runtime.

This paper formalizes the synthesis process of wiring signature-invariant (WSI) combinational circuit mutants. The signature /spl sigma//sub 0/ is defined by a reference circuit /spl eta//sub 0/, which itself is modeled as a canonical form of a directed bipartite graph. A wiring perturbation /spl gamma/ induces a perturbed reference circuit /spl eta//sub /spl gamma//. A number of mutant circuits /spl eta//sub /spl gamma/i/ can be resynthesized from the perturbed circuit /spl eta//sub /spl gamma//. The mutants of interest are the ones that belong to the wiring-signature-invariant equivalence class N/sub /spl sigma/0/, i.e. the mutants /spl eta//sub /spl gamma/i//spl isin/N/sub /spl sigma/0/. Circuit mutants /spl eta//sub /spl gamma/i//spl isin/N/sub /spl sigma/0/ have a number of useful properties. For any wiring perturbation /spl gamma/, the size of the wiring-signature-invariant equivalence class is huge. Notably, circuits in this class are not random, although for unbiased testing and benchmarking purposes, mutant selections from this class are typically random. For each reference circuit, we synthesized eight equivalence subclasses of circuit mutants, based on 0 to 100% perturbation. Each subclass contains 100 randomly chosen mutant circuits, each listed in a different random order. The 14,400 benchmarking experiments with 3200 mutants in 4 equivalence classes, covering 13 typical EDA algorithms, demonstrate that an unbiased random selection of such circuits can lead to statistically meaningful differentiation and improvements of existing and new algorithms.

Applying the Dmign of Experiments methodology to the evaluation of BDD van'able orden.ngalgon.thmshas yielded a number of conclusive Tesults.The methodology reiies on the rtient~y i~tTOdUCd equivalence classes of functionally petiurbed circuits that maintain logic invariance, , ...)-mintems of the original refeTence OT aTe urithin {1, 2 circuit function, abo maintaining entTopy-invan.ante.FOT some of the current vam.ableOTde~ng algom.thmsand tools, the negative raults include: (1) statistically significant sensitivity to naming of vatiables, (2) confirmation that a numbeT of variable orden.ngalgorithms aTe statistically equivalent to a random variable order assignment, and (3) obsemation of a statistically anomalous variable ordefl-ng behavioT of a wellknown benchmaTk circuit isomorphic class when analyzed un-deT a single and multiple outputs.On the positive side, the methodology supports a statistically significant mem.t evaluation of any newly introduced vatiable oTdem.ngalgon.thm,including the one bm.e~yintroduced in this papeT.