William D. Roome

dblp:73/6714 · DBLP profile ↗
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11ranked-venue papers
1as first author
0since 2021 · last 2012
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 7Computer networks · 2Systems, architecture and hardware · 1 · 1 first-authorDatabases, data management, data science and information retrieval · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
5 papers
Distributed systems · 49% Cloud and datacenter computing · 37% Performance modeling and evaluation · 8%
Computer networks
2 papers
Edge and fog computing · 90% Transport protocols and congestion control · 10%

Topics — the 21 heaviest of 25, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Distributed systems › distributed resource management
network-aware placement
0.112012
Network-aware service placement in a distributed cloud environment · SIGCOMM 2012
Cloud and datacenter computing › cloud service management
service placement
0.112012
Network-aware service placement in a distributed cloud environment · SIGCOMM 2012
Data models and query languages
object-oriented database
0.011994
OdeFS: A File System Interface to an Object-Oriented Database · VLDB 1994
Performance modeling and evaluation › simulation
concurrent simulation
0.011992
A General Framework for Concurrent Simulation of Neural Network Models · IEEE Trans. Software Eng. 1992
Performance modeling and evaluation › simulation
discrete-event simulation
0.011992
A General Framework for Concurrent Simulation of Neural Network Models · IEEE Trans. Software Eng. 1992
Performance modeling and evaluation
simulation
0.011992
A General Framework for Concurrent Simulation of Neural Network Models · IEEE Trans. Software Eng. 1992
Transport protocols and congestion control › transport protocols
high-speed transport protocol
0.011990
Design and implementation of a high-speed transport protocol · IEEE Trans. Commun. 1990
Transport protocols and congestion control › error control › automatic repeat request
selective repeat ARQ
0.011990
Design and implementation of a high-speed transport protocol · IEEE Trans. Commun. 1990
Parallel and multicore computing › parallel computing
parallel programming languages
0.011989
Experience with Multiple Processor Versions of Concurrent C · IEEE Trans. Software Eng. 1989
Parallel and multicore computing
parallel programming models
0.011989
Experience with Multiple Processor Versions of Concurrent C · IEEE Trans. Software Eng. 1989
Parallel and multicore computing
parallel programming runtimes
0.011989
Experience with Multiple Processor Versions of Concurrent C · IEEE Trans. Software Eng. 1989
Concurrent programming › message passing
ada rendez-vous
0.011988
Rendezvous Facilities: Concurrent C and the Ada Language · IEEE Trans. Software Eng. 1988
Programming languages and type systems
concurrent programming languages
0.011988
Rendezvous Facilities: Concurrent C and the Ada Language · IEEE Trans. Software Eng. 1988
Storage systems
file systems
0.011994
OdeFS: A File System Interface to an Object-Oriented Database · VLDB 1994
Performance modeling and evaluation › simulation › parallel and distributed simulation
parallel simulation
0.011992
A General Framework for Concurrent Simulation of Neural Network Models · IEEE Trans. Software Eng. 1992
Distributed systems
distributed programming
0.011989
Experience with Multiple Processor Versions of Concurrent C · IEEE Trans. Software Eng. 1989
Concurrent programming
synchronization
0.011988
Rendezvous Facilities: Concurrent C and the Ada Language · IEEE Trans. Software Eng. 1988
Electronic design automation › logic synthesis
finite state machine synthesis
0.011973
Algorithms for Multiple Shift Register Realizations of Sequential Machines · IEEE Trans. Computers 1973
Electronic design automation
logic synthesis
0.011973
Algorithms for Multiple Shift Register Realizations of Sequential Machines · IEEE Trans. Computers 1973
Electronic design automation › logic synthesis › sequential circuit synthesis
shift-register realization
0.011973
Algorithms for Multiple Shift Register Realizations of Sequential Machines · IEEE Trans. Computers 1973
Software testing › performance testing
load testing
0.011976
The LEAP Load and Test Driver · ICSE 1976

Methods — techniques the papers use, named apart from their topics

network status matching · 0.3placement algorithms · 0.1placement algorithm · 0.1object-oriented design · 0.0discrete-event simulation · 0.0concurrent processing · 0.0selective repeat · 0.0periodic state exchange · 0.0shared memory programming · 0.0message passing · 0.0
YearPublicationVenuePosition
2012 Network-aware service placement in a distributed cloud environment
abstract
We consider a system of compute and storage resources geographically distributed over a large number of locations connected via a wide-area network. By distributing the resources, latency to users can be decreased, bandwidth costs reduced and availablility increased. The challenge is to distribute services with varying characteristics among the data centers optimally. Some services are very latency sensitive, others need vast amounts of storage, and yet others are computationally complex but do not require hard deadlines on execution. We propose efficient algorithms for the placement of services to get the maximum benefit from a distributed cloud systems. The algorithms need input on the status of the network, compute resources and data resources, which are matched to application requirements.
Moritz Steiner, Bob Gaglianello, Vijay K. Gurbani, Volker Hilt, William D. Roome, Michael Scharf, Thomas Voith
SIGCOMM5
1994 OdeFS: A File System Interface to an Object-Oriented Database
Narain H. Gehani, H. V. Jagadish, William D. Roome
VLDB3
1992 Implementing Concurrent C
abstract
Abstract Concurrent C (C++) is a parallel superset of C (C++). Versions of Concurrent C have now been implemented for a variety of uniprocessors and multiprocessors. We first implemented a uniprocessor version of Concurrent C correctly anticipating that it would be relatively easy to extend the uniprocessor implementation to run on multiprocessors. Concurrent C is translated to C. The generated C code contains calls to the C library implementing the Concurrent C run‐time system. This paper describes the ‘hard core’ details of the Concurrent C implementation: the specifics of process states, the data structures used, the library functions, and the C code generated for various Concurrent C constructs. We also give an overview of the Concurrent C facilities and of the uniprocessor, distributed and shared‐memory multiprocessor implementations.
Narain H. Gehani, William D. Roome
Softw. Pract. Exp.2
1992 A General Framework for Concurrent Simulation of Neural Network Models
abstract
The analysis of complex neural network models via analytical techniques is often quite difficult due to the large numbers of components involved and the nonlinearities associated with these components. The authors present a framework for simulating neural networks as discrete event nonlinear dynamical systems. This includes neural network models whose components are described by continuous-time differential equations or by discrete-time difference equations. Specifically, the authors consider the design and construction of a concurrent object-oriented discrete event simulation environment for neural networks. The use of an object-oriented language provides the data abstraction facilities necessary to support modification and extension of the simulation system at a high level of abstraction. Furthermore, the ability to specify concurrent processing supports execution on parallel architectures. The use of this system is demonstrated by simulating a specific neural network model on a general-purpose parallel computer.>
Gregory L. Heileman, Michael Georgiopoulos, William D. Roome
IEEE Trans. Software Eng.3
1990 Design and implementation of a high-speed transport protocol
abstract
The design, analysis, and implementation of an end-to-end transport protocol that is capable of high throughput consistent with the evolving high-speed physical networks based on fiber-optic transmission lines and high-capacity switches are presented. Unlike current transport protocols in which changes in control/state information are exchanged between the two communicating entities only when some significant event occurs, this protocol exchanges relevant and full state information periodically and frequently. It is shown that this reduces the complexity of protocol processing by removing many of the procedures required to recover from network inadequacies such as bit errors, packet loss, and out-of-sequence packets and makes it more amenable to parallel processing. Also, to increase channel utilization in the presence of high-speed, long-latency networks and to support diagrams, and efficient implementation of the selective repeat method of error control is incorporated in the protocol. An implementation using a Motorola 68030-based multiprocessor as a front-end processor is described. The current implementation can comfortably handle 10-15 kpackets/s.>
Arun N. Netravali, William D. Roome, Krishan K. Sabnani
IEEE Trans. Commun.2
1989 Experience with Multiple Processor Versions of Concurrent C
abstract
Concurrent C, a superset of C providing parallel programming facilities, is considered. A uniprocessor version of Concurrent C was first implemented. After experience with this version, the Concurrent C implementation was extended to run on two types of multiple processor systems: a set of computers connected by a local area network (the distributed version) and a shared-memory multiprocessor (the multiprocessor version). Experience with implementing and using these versions of Concurrent C is described. Specifically, the language changes triggered by the multiple processor implementations, some sample programs, a comparison of the execution times on various systems, and the suitability of these multiple processor architectures are discussed.>
Robert F. Cmelik, Narain H. Gehani, William D. Roome
IEEE Trans. Software Eng.3
1988 Concurrent C++: Concurrent Programming with Class(es)
abstract
Abstract C++ and Concurrent C are both upward‐compatible supersets of C that provide data abstraction and parallel programming facilities, respectively. Although data abstraction facilities are important for writing concurrent programs, we did not provide data abstraction facilities in Concurrent C because we did not want to duplicate the C++ research effort. Instead, we decided that we would eventually integrate C++ and Concurrent C facilities to produce a language with both data abstraction and parallel programming facilities, namely, Concurrent C++. Data abstraction and parallel programming facilities are orthogonal. Despite this, the merger of Concurrent C and C++ raised several integration issues. In this paper, we will give introductions to C++ and Concurrent C, give two examples illustrating the advantages of using data abstraction facilities in concurrent programs, and discuss issues in integrating C++ and Concurrent C to produce Concurrent C++.
Narain H. Gehani, William D. Roome
Softw. Pract. Exp.2
1988 Rendezvous Facilities: Concurrent C and the Ada Language
abstract
The concurrent programming facilities in both Concurrent C and the Ada language are based on the rendezvous concept. Although these facilities are similar, there are substantial differences. Facilities in Concurrent C were designed keeping in perspective the concurrent programming facilities in the Ada language and their limitations. Concurrent C facilities have also been modified as a result of experience with its initial implementations. The authors compare the concurrent programming facilities in Concurrent C and Ada and show that it is easier to write a variety of concurrent programs in Concurrent C than in Ada.>
Narain H. Gehani, William D. Roome
IEEE Trans. Software Eng.2
1986 Concurrent C
Narain H. Gehani, William D. Roome
Softw. Pract. Exp.2
1976 The LEAP Load and Test Driver
Ted A. Dolotta, J. S. Licwinko, R. E. Menninger, William D. Roome
ICSE4
1973 Algorithms for Multiple Shift Register Realizations of Sequential Machines
abstract
This paper considers the problem of realizing synchronous sequential machines with shift registers. The problem is approached in two steps.
William D. Roome, H. C. Toorng
IEEE Trans. Computers1