Article Interconnect analysis: from 3-D structures to circuit models Share on Authors: M. Kamon Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , N. Marques Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , Y. Massoud Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , L. Silveira Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , J. White Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 910–914https://doi.org/10.1145/309847.310097Online:01 June 1999Publication History 8citation278DownloadsMetricsTotal Citations8Total Downloads278Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate three-dimensional interconnect models. In this paper, we describe an integral equation aproach to modeling the impedance of inter-connect structures accounting for both the charge accumulation on the surface of conductors and the current traveling in their interior: Our formulation, based on a combination of nodal and mesh analysis, has the required properties to be combined with Model Order Reduction techniques to generate accurate and guaranteed passive low order Interconnect models for efficient inclusion in standard circuit simulators. Furthermore, the formulation is shown to be more flexible and efficient than previously reported methods.

As VLSI circuit speeds have increased, the need for accurate three-dimensional interconnect models has become essential to accurate chip and system design. In this paper we describe an integral equation approach to modeling the impedance of interconnect structures accounting for both the charge accumulation on the surface of conductors and the current traveling along conductors. Unlike previous methods, our approach is based on a modified nodal analysis formulation and can be used directly to generate guaranteed passive low order interconnect models for efficient inclusion in a standard circuit simulator.

In this paper we describe a computationally efficient approach to generating reduced-order models from PEEC-based three-dimensional electromagnetic analysis programs. It is shown that a recycled multipole-accelerated approach applied to recent model order reduction techniques requires nearly two orders of magnitude fewer floating point operations than direct techniques thus allowing the analysis of larger, more complex three-dimensional geometries.