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T. Y. Tee

dblp:73/8562 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2009
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Electronic design automation · 50%

Topics — the 1 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › packaging
wafer-level chip-scale packaging
0.112009
Overview of Board-Level Solder Joint Reliability Modeling for Single Die and Stacked Die CSPs · Proc. IEEE 2009

Methods — techniques the papers use, named apart from their topics

finite element modeling · 0.1
YearPublicationVenuePosition
2009 Overview of Board-Level Solder Joint Reliability Modeling for Single Die and Stacked Die CSPs
abstract
Modeling can efficiently investigate the reliability of new packages, saving time, manpower, and cost for conducting actual tests; A good model is useful for short time-to-market. In this paper, only journal and technical magazine papers are reviewed, many of which report modeling analyses of single die and/or stacked die chip-scale packages. They are summarized regarding the methods, design parameters, and/or results. Brief comparisons are provided on similarities and differences of the effects of the common design parameters on solder-joint reliability. The effects of variations in materials, package designs, the number of dies, test conditions, and board geometry can be investigated efficiently by thermal cycling modeling or drop test modeling.
T. Y. Tee
Proc. IEEE2