This paper presents a high-bandwidth memory (HBM) PHY interface employing a reconfigurable differentiator-based crosstalk cancellation (XTC) scheme to mitigate coupling noise arising in high-density silicon interposer channels. By introducing a novel analysis of RC-dominant channels from the perspective of group delay, the proposed XTC achieves precise delay matching by optimal differentiator parameter selection, without requiring additional hardware. Furthermore, the self-loading induced by multiple-aggressor XTC is compensated by reconfiguring the XTC scheme into a bandwidth extension scheme in which the bi-directional signaling nature of HBM interface is leveraged. Additionally, the merged adder with multiple-XTC and decision-feedback equalization (DFE) is proposed to provide improved offset and power performance. Fabricated in a 28-nm CMOS process, the prototype transceiver achieves an edge density of 15 Tb/s/mm and energy efficiency of 0.53 pJ/bit with high-density on-chip channels of 7.5-dB Nyquist loss. The proposed XTC technique reduces the crosstalk-induced jitter (CIJ) by four aggressors by 72.4% at a signal-to-crosstalk ratio of 0.45 dB, achieving an eye-opening of 0.42 UI at a$10^{-12}$bit error rate (BER).

High-bandwidth memory (HBM) has enabled substantial advancements in bandwidth-intensive applications, including large-scale artificial intelligence models. HBM is typically integrated with other systems-on-chip (SoCs) through a silicon interposer, and the primary bottleneck in aggressively scaling the bandwidth in next-generation HBM systems stems from significant crosstalk caused by closely spaced, high-density parallel interconnects in the interposer. While crosstalk avoidance code (CAC) has emerged as a promising solution, prior CAC schemes suffer from low bit efficiency and considerable hardware overhead. This article proposes an efficient CAC scheme, WITCH, which employs a novel weighted coding strategy. Unlike prior approaches that consider all channels identically, WITCH assigns different weights to channels based on their relative positions in the array, enabling more bit-efficient crosstalk suppression. We also present WITCH with additional shielding (WITCH-AS), an extension of WITCH that incorporates additional shielding to further reduce crosstalk levels. Our coding schemes achieve high bit efficiency, up to 17.3% higher than state-of-the-art techniques while providing an identical level of crosstalk reduction. Simulation results using an industry-proven channel model demonstrate that WITCH and WITCH-AS improve eye height by 10.1%–49.4% and 17.1%–51.1%, respectively. Furthermore, we propose an area- and energy-efficient hardware implementation that can be integrated into real-world HBM systems. The design reduces area and critical path delay by 31.0% and 28.2%, respectively, compared with conventional designs. Finally, we propose a compatible simultaneous switching output (SSO) noise mitigation technique that can be seamlessly integrated into WITCH to further enhance signal integrity under high-speed, high-density operating conditions.

High bandwidth memory (HBM) has enabled a breakthrough in bandwidth-bound applications, including large-scale artificial intelligence models. HBM is typically connected to other SoCs through a silicon interposer. However, the increasing density of the parallel interconnect wires incurs significant amount of crosstalk, hindering bandwidth improvement in the next-generation HBMs. While Crosstalk Avoidance Code (CAC) has emerged as a solution to mitigate crosstalk, prior CAC schemes suffer from low bit efficiency and significant hardware overhead. This paper proposes an efficient CAC scheme, WITCH. It employs a new coding system, weighted coding, which gives a different emphasis to each channel according to its relative position in the channel array. This enables crosstalk reduction with higher bit efficiency than prior CACs treating all channels in the array equally. The extended version of WITCH, WITCH-AS, is also proposed with additional shielding for further crosstalk reduction. Our coding system shows high bit efficiency of 91.2--91.7% and 84.3--84.6% for WITCH and WITCH-AS, which is up to 20.8% higher than the state-of-the-art schemes while preserving the same crosstalk level reduction. We have shown through simulations using an industry-proven channel model that WITCH and WITCH-AS improve the eye heights by 10.1--49.4% and 17.1--51.1% respectively. In addition, this paper presents an efficient hardware implementation of our coding schemes which shows 28.2% lower critical path delay and 31.0% smaller area than conventional implementation, proving itself a practical solution for HBMs.

The chip industry is undergoing a market transition from mass production to mass customization. Rapid market changes require agile responses and diversified product designs, particularly in interface circuits managing chip-to-chip communication. To facilitate these shifts, this paper proposes a machine learning-based method for rapidly and accurately predicting and analyzing the performance of high-speed transceivers, along with an evaluation methodology utilizing the proposed approach. Especially, using the process technology information as input in the dataset, this is the first work to predict the performance of a design across different technologies, which will be invaluable in architecting and optimizing designs during the early stages of development. By simulating each functional block, we gather a dataset for parameterized design and performance and incorporate device characteristics from lookup tables. The transmitter, which operates like digital circuits, is trained using parameterized signals with a DNN, while the receiver, containing analog blocks and feedback structures, employs hybrid LSTM-DNN learning with time-series input and output. Our model, trained with a 40 nm design, demonstrates high accuracy in predicting performance even with different foundries and technologies. The majority of performance parameters show an R2value exceeding 0.9, indicating strong predictive accuracy under varying conditions. This method provides valuable insights for early-stage design optimization and process technology scaling, offering potential for broader applications in circuit design areas.

This paper describes a design methodology for CMOS silicon photonic interconnect ICs according to CMOS technology scaling. As the CMOS process is scaled, the endurable voltage stress and the intrinsic gain of the CMOS devices are reduced; therefore, a design of the highswing transmitter and high-gain receiver required at the silicon photonic interface becomes much more challenging. In this paper, a triple-stacked Mach-Zehnder modulator driver and an inverter-based transimpedance amplifier with inductive feedback are proposed, and the robustness of the proposed designs is verified through Monte Carlo analyses. The prototype ICs are fabricated using a 65-nm CMOS technology. The transmitter exhibits a 6 Vpp output swing, 98-mW power consumption, and 0.04-mm2active area at 10 Gb/s. The receiver was verified with a commercial photodetector, and it exhibits a 78-dBΩ gain, 25.3-mW power consumption, and 0.18-mm2active area at 20 Gb/s.

This paper describes a CMOS interface circuit for silicon photonics. 20-Gb/s operation of an optical receiver front-end circuit is demonstrated using an optical signal applied to the optical front-end. The transimpedance amplifier (TIA) is based on an inverter with resistive and inductive feedback for low power consumption and frequency compensation. A negative capacitance generation is employed in the limiting amplifier (LA) for bandwidth extension. The combined TIA and LA block exhibits a transimpedance gain of 78 dBΩ and a bandwidth of 11 GHz. The TIA and the LA block consume 1.3 mA and 24 mA at 1 V supply voltage, respectively.

In this work, a 12.5-Gb/s trans-impedance amplifier (TIA) with capacitive peaking, limiting amplifier (LA) based on the Cherry-Hooper amplifier, and high-voltage laser/modulator driver are proposed in 0.13-μm CMOS process. The TIA and the LA operate without any inductors, and the TIA achieves a trans-impedance gain of 52.9-dBΩ and a bandwidth of 14.3GHz. The TIA and the LA use the negative Miller effect to extend the bandwidth without using any inductors. The core layout occupies an area of only 35*150 μm2. The laser/modulator driver of the transmitter drives the capacitance of the Mach-Zehnder modulator which contributes around 1.2pF. Using only thin MOS devices, the output swing of the driver exceeds 2.4V. The measurement results show the overall operating speed of 12.5-Gb/s.

This paper presents an IEEE 1588-2008 adapter that provides existing Gigabit Ethernet equipment with the functionalities required to clock synchronization on the order of sub-microsecond. To compensate the time error caused by the queuing delays in the Gigabit Ethernet equipment, the adapter measures the residence time and runs the peer delay mechanism for the equipment. Major functional blocks including the clock synchronization cores, Media Access Controls (MACs), and frame buffers have been integrated into a 21 mm2silicon chip in 0.18 μm CMOS process. Experimental results show that the end devices can be synchronized within ±20 ns by simply attaching the proposed IEEE 1588-2008 adapters to the ordinary switches that connects the end devices.