This paper presents a fully integrated NMOS stimulator using a hybrid dynamic bulk biasing technique (HDBT) and a charge-pump-like control technique (CCT) in a 180-nm bulk CMOS technology. HDBT integrates terminal-voltage-dependent and logic dynamic bulk biasing to set the bulk bias voltage according to the electrode voltage. CCT adds a DC voltage to the gate terminal through a diode and capacitor to help turn on the NMOS transistor. It helps turn off the transistor by shorting the source and gate terminals together and applying two diodes across the drain and source terminals. To achieve an electrode voltage higher than the breakdown voltage of substrate diode ($V_{\mathrm {BD}}$) with an independent power supply, a high voltage tolerant switch is proposed with HDBT and CCT. A high voltage interface is also proposed, utilizing the capacitor adaptive biasing, to overcome the limitation of$V_{\mathrm {BD}}$between the high and low voltage domains and to accommodate the variation of electrode voltage. Fabricated in a 180-nm standard CMOS technology, the stimulator achieves a maximum electrode voltage ($V_{\mathrm {E,MAX}}$) of 18.74V under a 3.3-V supply, with a highest$V_{\mathrm {E,MAX}}$/$V_{\mathrm {BD}}$ratio of 1.27 than state-of-the-art stimulators, including non-standard technology designs. In a continuous output test mode over 10million cycles, the variation of$V_{\mathrm {E,MAX}}$is less than 150mV. The measured maximum residual voltage on the capacitor is 13.55mV.

This brief presents an area-efficient noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) employing a parallel-delayed sampling (PDS) technique. PDS samples the residual voltages from multiple ADC conversion cycles to increase the NS effect, without the need for large integration capacitors of the typical cascaded passive integrators. A preamplifier is placed between the sampling capacitors and the integrator to avoid signal attenuation, while further reducing the area of the integrator. PDS and preamplifier introduce two left-half-plane poles to the noise transfer function (NTF) to boost the NS effect, while reducing the impact of the parasitic capacitance to essentially enhance the robustness. A prototype 9-bit NS-SAR ADC is designed in a 130-nm CMOS process. At an oversampling ratio (OSR) of 16, the proposed PDS NS-SAR ADC achieves 80.93-dB peak signal to noise and distortion ratio (SNDR) and provides 4.2 NS/area efficiency factor. It consumes a power of$23.46~\mu $W over a bandwidth of 19.53 kHz, achieving a Schreier figure of merit (FoM${}_{\mathrm {S}}$) of 170.13 dB.

This brief presents a CMOS inverter (INV)-based amplifier with local and system dual common-mode feedback (CMFB) loops through paralleled pseudo transconductors (PTs) for multichannel neural signal recording. The PT-INV forms a DC-coupled input to ensure a high input impedance, and local and system dual CMFB loops are introduced through the paralleled PT terminals of the INV. The local CMFB (L-CMFB) with the capacitor-reused topology not only reduces the die area and increases the differential-mode (DM) gain but also reduces the common-mode (CM) gain. The system CMFB (S-CMFB) loop detects the multiple CM outputs, and further increases the overall CMRR. The proposed PT-INV based instrumentation amplifiers (IAs) with dual CMFB loops are fabricated in a 0.18-$\mu $m CMOS process, and an overall CMRR of 87dB is achieved with a compact single-channel core area of 0.02mm2.

This paper presents an ultra-low power third-harmonic blocker-tolerant receiver (RX) using dual current-reuse N-path low noise amplifier (LNA) and band-switchable balun. The proposed RX front-end uses I&Q third-harmonic mixing based on non-overlapping 12-phase local oscillator (LO), which reduces the operating frequency and tunable range of RF source by 6 times to save the power of LO generator. A dual current-reuse N-path LNA is proposed to reduce the LNA power consumption by half without sacrificing out-of-band suppression. Moreover, the trade-off between bandwidth matching and high-Q selectivity is broken under extremely low power consumption by combining band-switchable balun and N-path LNA. The RX is designed in a 40 nm CMOS process with a core area of 0.69 mm2. The simulated results indicate that the RX achieves wideband tunable high-Q selectivity from 1.6 to 3.2 GHz with the double sideband (DSB) NF from 3.8 to 4.4 dB and +12.2 dBm out-of-band (OB) IIP3 at 100 MHz offset. Over the frequency range of interest, total RX power consumption is 1.52 to 1.92 mW, with the LO driver requiring only 0.19 mW/GHz.

This paper presents a hybrid all-NMOS rectifier with two gate-biasing techniques to extend the power dynamic range (PDR) for wireless power transfer. The proposed hybrid rectifier combines the strengths of the cross-connected (CC) and diode-based (DB) configurations, achieving both a high forward current and a small reverse current along the PDR. Additionally, two separate gate-biasing techniques are employed to optimize the gate bias voltage for the gate-biased-CC and gate-biased-DB parts, respectively. All transistors in the rectifier are NMOS transistors, which can minimize the total area when extended to multi-stage configurations. The circuit is implemented in a 180-nm CMOS process, occupying an area of 0.195 mm2. Experimental results show a sensitivity of -10.3 dBm with a 1 MΩ load and a peak power conversion efficiency of 78.6% at -7.4 dBm with a 3 kΩ load. In addition, the proposed rectifier achieves a PDR greater than 22.3 dB with loads below 5 kΩ.

This paper aims to the remote synchronous control for complex networks with amplify-and-forward (AF) relays. Firstly, the AF relay dynamic with random noise is integrated into the control signal transmission. Secondly, the complex networks incorporating an AF relay is converted into the sliding control mode (SMC), which robustly addresses unknown disturbances among the nodes to achieve synchronous states. Thirdly, an adaptive gain mechanism based on the equivalent value of sign function of SMC is proposed to estimate the disturbance amplitude, hence mitigating the chattering of SMC. Finally, the illustrative simulation demonstrated the effectiveness of proposed methodology.

An oscillator-based reconfigurable modulator is proposed to support multi-mode and fast modulation. A direct-modulation structure composed of the cross-coupled oscillator with the fast-switched film bulk acoustic resonator (FBAR) is used to enhance the frequency stability under fast OOK/BFSK modulation. To avoid extra phase-reversal circuitry, a polarity-swapped switching structure is employed in the differential branches of the modulator to achieve energy-efficient BPSK modulation, and this structure is also reused as a buffer stage for OOK/BFSK modulation to avoid the loading effect. In addition, an adaptive fast-switching technique is also proposed to improve OOK/BFSK modulation data rate and energy efficiency. The modulator is fabricated in a 180 nm CMOS technology. The free-running oscillation frequencies with two FBARs are 962 MHz and 990 MHz, and the measured phase noises are -137.3 dBc/Hz@1MHz and -137.1 dBc/Hz@1MHz, respectively. For OOK/BFSK/BPSK modulation, the proposed modulator demonstrated 280/325/67.6 pJ/bit energy efficiency and 5.63/4.20/5.55 % rms EVM with 10/10/50 Mbps data rates.

This article presents a Gm-controlled inverter (GC-INV) based amplifier with multiple common-mode feedback (CMFB) loops for multi-channel bio-signal recording. The GC-INV forms a DC-coupled input to ensure a high input impedance. The multi-CMFB, including twin local (TL), regional system (RS), and averaged system (AS) CMFB loops, is introduced through the paralleled GC terminals to provide multiple feedback paths. The TL-CMFB with capacitor-reused topology not only reduces the die area and increases the differential-mode gain, but also reduces the common-mode (CM) gain. The RS-CMFB mitigates the common-mode interference (CMI) due to the mismatch of the CM feedback paths. The AS-CMFB further mitigates the accumulated CMI from CM sampling paths. These CMFB loops avoid the design trade-off between the intrinsic CMRR and the efficiency of area and power. The proposed GC-INV based amplifier with multi-CMFB is fabricated in a 0.18-$\mu $m CMOS technology. It achieves an intrinsic CMRR of 97 dB, TCMRR of 78 dB, and the single-channel INV consumes a chip area of 0.008 mm2.

This paper presents a monopolar neural stimulator using dynamic current replication technique based on switched-capacitor sampling. It employs dynamic current mirror circuits as the current source and the current sink to overcome the impact of process variation on current matching, achieve good charge balance and ensure the security of the monopolar neural stimulator. The proposed monopolar stimulator is implemented with a 0.18-μm 1.8 V/3.3 V standard CMOS process. The simulated results indicate that the current mismatch between the cathodic and anodic current is less than 0.21%, and the charge mismatch is below 0.33% within the entire stimulus current range (0.3 mA ~ 3 mA). The corresponding maximum residual average DC current error with shorting electrode discharge is less than 1 nA.

This paper presents a self-powered parallel synchronized switch harvesting on inductor (P-SSHI) active rectifier with an energy-efficient adaptive switch control circuit. The energy-efficient adaptive switch control circuit reuses comparators within the active rectifier for both zero-crossing detection and voltage flipping detection, simplifying the switch control module. The proposed active rectifier incorporates an active diode and a MOSFET within each energy transfer path to mitigate the forward voltage drop across rectifying elements. The proposed P-SSHI circuit which includes a diode in each voltage flipping path shows high adaptability to different inductances. All the auxiliary circuits are powered by the storage capacitor. The proposed circuit is designed in 180 nm CMOS process, and the total occupied chip area is 0.18 mm2. The power dissipation of the switch control module is only 0.15 μW, owing to its simplicity. The simulation results show that the proposed design achieves a high voltage flipping efficiency of 85.4%. The maximum output power is 5.5 times greater than that of the ideal full-bridge rectifier.

This paper presents a fully integrated stimulator using a dynamic bulk biasing technique and a dynamic control scheme in a 180-nm bulk CMOS technology. Unlike the conventional bulk biasing method, the bulk bias voltage is dynamically set according to the different stimulation phases. It avoids the underlying leakage current paths, and improves the maximum stimulation voltage compliance (MSVC). Together with dynamic bulk biasing scheme, a high voltage interface is designed to overcome the limitation of the breakdown voltage of the substrate diode ( V$_{\mathbf{BD}}$) between the high and low voltage domains. An all-NMOS dynamic charge pump is also proposed as a dynamic power supply above V$_{\mathbf{BD}}$and provides dynamic bulk-biasing voltages. Fabricated in a 180-nm standard CMOS technology, the stimulator achieves an MSVC of$\pm$16.5 V under a 3.3-V supply, and the achieved MSVC is$\sim$1.11 times higher than the V$_{\mathbf{BD}}$($\sim$14.8 V) of the substrate diode. The stimulator is also measured in a continuous output test mode for over 10 million cycles, the variation of$\vert$MSVC$\vert$is less than 200 mV.

This brief proposes a parallel multiresidual (PMR) integrator to enhance the noise-shaping (NS) effect for successive approximation register (SAR) analog-to-digital converter (ADC). The PMR employs passive integrators in parallel to simultaneously integrate the average result of the multiple sequential residual voltages. The proposed PMR technique provides an alternative scheme to enhance the NS rather than increasing the order of the integrator to suppress the instability and power. A prototype 7-bit second-order NS-SAR ADC is designed and simulated in a 130-nm CMOS process. PMR increases the effective number of bits (ENOBs) to 10.6 bit, which enhances the NS effect of 3.6 bit. It achieves a peak signal-to-noise and distortion ratio (SNDR) of 65.84 dB over a bandwidth of 1.3 kHz at the oversampling ratio (OSR) of 16.

This paper presents an ultra-low power 802.11ba receiver for Internet of things (IoT) devices. A low-power third-harmonic mixer based on a 6-phase non-overlap local oscillator (LO) operating at 1/3 RF frequency is proposed to improve the out-of-band rejection. The analog finite-impulse-response (AFIR) filter in the baseband is designed for better adjacent channel rejection (ACR) while maintaining the low power consumption. A tunable tapped-capacitor resonator is designed to provide the passive voltage gain and input matching with zero power consumption. The simulation results show that the proposed receiver achieves a sensitivity of -93.5 dBm with the conversion gain of 51 dB. It can achieve$\leq-\mathbf{15}\mathbf{dB} \ \text{S}_{11}$at different process corners via frequency tuning. The simulated ACR is ~93 dB for 802.11ba standard. The receiver consumes a total power of$\mathbf{197}\ \boldsymbol{\mu} \mathbf{W}$, and the core area is 0.25 mm2.

In this paper, a high global efficiency OOK transmitter (TX) working at 400–460 MHz is proposed by utilizing third-harmonic edge-combining technique for low power biomedical applications. The operation frequency of the proposed TX before the third-harmonic edge-combiner (THEC) is 1/15 of the output RF frequency and 1/3 of the traditional edge-combiner-based TX. The multi-phase signals used for edge combiner (EC) are generated by a delay-locked loop (DLL) at a relative low frequency, which significantly reduces the overall TX power consumption. The TX is designed in 55-nm CMOS process with a core area of 0.02 mm2, the proposed TX consumes a DC power of$98.75\ \mu\mathrm{W}$under a 0.8 V supply voltage. The simulated output power is −14 dBm with 20 Mbps OOK data. The TX achieves a 41% global efficiency and a 4.94 pJ/bit energy efficiency, respectively.

This paper proposes a dual-path CMOS RF-to-DC rectifier operating at 2.45-GHz with an ultra-wide high power conversion efficiency (high-PCE) input range. A new rectifier based on all NMOS rectification devices (all-NMOS) is proposed for high-power path and a modified cross-connected (CC) rectifier is designed for low-power path. The control signal for path switching is adaptively generated by auxiliary circuits without external reference or supply. The input power range with high-PCE is extended by the proposed architecture to meet the various application scenarios of energy harvesting. Implemented in a 0.18-μm standard CMOS technology, the proposed dual-path rectifier achieved a sensitivity of −20.7dBm, and it has two peak PCEs of 57% and 62% at −15dBm and 1.6 dBm, respectively. Furthermore, the PCE of the proposed dual-path rectifier can be maintained above 20% with a 27 dB input range from −22 to 5 dBm when operating at 2.45-GHz with a 50-k$\Omega$ load.

This paper presents an inductor-less RF transmitter (TX) based on harmonic-rejection edge combiner (HREC) and delay-locked loop (DLL) to suppress the $3^{\mathrm{rd}}/5^{\mathrm{th}}$ harmonics for low-power biomedical applications. The proposed HREC utilizing a resistance-divider technique not only achieves $9\times$ frequency multiplication but also simultaneously cancels the $3^{\mathrm{rd}}/5^{\mathrm{th}}$ harmonics by shaping the output voltage waveform. To reduce the power consumption, the multi-phase input signals for the HREC are generated by a DLL at a relative low frequency. The TX is designed in a 65-nm CMOS process with a core area of 0.05 mm2. The simulation results show that the proposed TX achieves the 3rdand 5thharmonics rejection > 40 dBc and > 52 dBc, respectively. It delivers a −16 dBm output power to a 50 $\Omega$ load without using any on- and off-chip inductors. The TX consumes a total DC power of 1.1 mW from a supply voltage of 1 V.

This paper presents two high-efficiency charge pumps (CPs) by utilizing the gate voltage boosting technique (GVBT). Unlike traditional bulk-CMOS and all-NMOS CPs, an input bias voltage is independently applied to the gate terminal, and it improves the current driving capability without the need of large pumping capacitors or high-frequency clocks. Meanwhile, the GVBT decouples the state of transistors from the clocks connected to the pumping capacitor, and it can eliminate the reversion loss in both main and auxiliary circuits. Fabricated in a 0.18-$\mu \text{m}$standard CMOS technology, the single-stage all-NMOS CP achieved a maximum output voltage of 6.589 V and a peak power efficiency of 80.08%. We also implemented the bulk-CMOS CP with GBVT for comparison, the single-stage all-NMOS CP achieved$\sim 1.24\times $more output voltage than the bulk-CMOS CP under a load current of 1.5 mA. The voltage errors of the all-NMOS CP between the analytical and the measured results are less than 7%.

This paper presents the high-efficiency charge pumps (CPs) that eliminate the reversion loss by using gate voltage boosting technique. First, a 6-phase bulk-CMOS CP with enhanced gate voltage is designed to reduce the reversion loss. Second, an all-NMOS CP is also demonstrated to improve the current driving capability and to break the limitation of the substrate diode breakdown voltage. The chip is designed with a 0.18-μm standard CMOS technology. As a result, the single-stage bulk-CMOS CP achieves a maximum output voltage and peak power efficiency of 6.595V and 84.2%, respectively. Moreover, the all-NMOS CP achieves ~1.2× more output voltage than the bulk-CMOS CP at 1.5mA load current.