A truly Medical Implantable Communications Service (MICS) band compliant transmitter for biomedical applications, covering all ten channels in 402-405MHz is presented in this paper. The transmitter consists of a Phase Locked Loop(PLL) with rail to rail quadrature output, a passive mixer and a power amplifier (PA). The power consumption of the transmitter is 425μW at 1.2 V, and consumes only 7.1 nJ of energy per bit transmitted. The overall global efficiency of the transmitter is 19.3 %. This transmitter can account for PVT variations. The proposed transmitter meets all the federal communications commission (FCC) requirements for the MedRadio band. This proposed work is implemented in a 180nm CMOS process.

Implantable biomedical devices are typically battery operated. Therefore they normally have stringent constrains on power consumption and size. This paper presents a low power 64-point, 16-bit fixed-point Fast Fourier Transform(FFT) processor design. Bit-serial logic was used in the design to achieve low power while maintain sufficient performance for biomedical applications. The proposed FFT design was implemented in a commercial 0.18um CMOS process with a power supplier of 1.8V and running at 50MHz clock rate. The power consumption of 14mW with 0.55Mpoints/s signal throughput is achieved.

Biomedical devices are often battery operated and require low power consumption. As biomedical devices increase in complexity to include multiple functions such as signal processing and data storage, the constraint on power consumption becomes a larger issue. This paper presents a low power design for a decimator as part of a sigma-delta ADC for biomedical application in a commercial 0.18um CMOS process. To make the design low power, it makes use of a bit-serial architecture, a low supply voltage of 0.9V and a clock rate of 1MHz.

Storage arrays are widely used in integrated biosensor systems to store detected signals before and after they are processed. As integrated biosensor systems often require very low power consumption to extend battery life and to maintain low cost, power consumption for storage arrays in integrated biosensor systems should be kept low, whereas the speed requirement is usually not high such that state-of-the-art IC technology is not usually needed. This paper presents the results of our investigation of designing low power memory structures in sub 1-V operation with high reliability for biosensor systems. Rather than using the state-of-the-art 45nm/32nm technology, 0.18 um CMOS technology is used for the design to keep the overall cost down while achieving read and write performance of 200MHz cycle rate. The results show that the use of body back bias in systems with low supply voltage can improve memory's static noise margin (SNM) and memory write performance by as much as 25%.

Clock distribution in the multi-gigahertz range is getting increasingly difficult due to more stringent requirements for skew and jitter on one hand and the deteriorating supply voltage integrity and process variation on the other hand. Global clock network, especially in nanometer CMOS designs with ever increasing die sizes, has become a prominent performance limiter. A potential alternative to traditional interconnect technology for achieving clock distribution beyond 10 GHz while maintaining required skew and jitter budgets is using on-chip optical interconnects. A practical on-chip optical clocking system must be CMOS compatible in order to provide attractive cost effectiveness for system level integration and ease of manufacturing. This paper presents the design of a fully CMOS compatible optical clock distribution and recovery system in a 3.3 V, 0.35-$\mu$m CMOS process. Experimental results from the test chip prove the feasibility of providing optical-electrical interface in devices and circuits in a fully CMOS compatible manufacturing environment. Although the test chips were designed in a mature CMOS process technology and the measured performance is low, the test chips demonstrated the feasibility of on-chip optoelectronic integration with fully CMOS compatible process. On-chip optical clock distribution is one of the natural applications of fully CMOS compatible on-chip optical interconnect technology.

Radiation-induced soft errors on large-scale integrated circuits are becoming increasingly problematic as device sizes are scaled down, operating voltages are reduced, and node capacitances shrink. Therefore, chip reliability has become a big issue in modern VLSI design and the importance of detecting soft error in combinational logic circuits has been recognized. In this paper a method incorporating two error detecting methods, parity check and shadow latch, is presented. The results show that the proposed method combines the best of both previously proposed methods and achieves the soft error rate reduction of 70% with 50% cost overhead for random logic blocks, providing a better cost return for using either method along.

Early design phase space exploration, power validation and performance estimation will enable faster design convergence and shorter time-to-market. System level models based on physical design parameters, in-situ macro models and background SPICE simulation improves overall model accuracy. This paper describes a pareto analysis methodology for design target generation to meet time-to-market constraint; illustrating design choice generation algorithm and a test circuit SPICE validation. Power and performance centric design solutions (targets) that are not obvious to the designers are explored. Pareto analysis yielded power centric design target that improved both system power consumption and performance by 19.6% and 6.3% respectively. Performance centric design target improved system level performance and power by 11.7% and 1.63% respectively.

The economics of continued scaling of silicon process technologies beyond the 90-nm node will face significant challenges due to variability. The increasing relative magnitude of within die process variations will cause power-frequency distributions to widen, thus, reducing manufacturing yields. Mitigating the effects of these process variations can be done by using the proposed individual well-adaptive body biasing (IWABB) scheme of locally generated body biases. IWABB allows for highly localized circuit optimizations with very little overhead in silicon area and routing resources. We present two algorithms to find near-optimal configurations of these biases which can be applied as postsilicon tuning. The proposed IWABB scheme can improve an initial yield from 12% to 73%

Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of different inputs on a logic gate ever closer to each other. The traditional method of static timing analysis assuming single input switching is no longer adequate enough to capture gate level delays accurately. Gate delay models considering multiple input switching are needed for DSM chips. We propose a new method of systematically modeling gate delays using the high dimensional model representation (HDMR) method. The proposed method models gate delays with respect to the relative signal arrival times (RSAT) of its inputs. The systematic nature of the proposed algorithm allows gate delay characterization with more inputs switching close to each other. This paper will show, for the first time, gate delay models of up to 5 inputs. In addition, the proposed model is extended to allow the input signal slope and process variations to be taken into account for statistical static timing analysis. Our results show that the proposed HDMR model gives an error between 2.2% to 12.9% for a variety of static and dynamic logic gates as compared to SPICE results, depending on the number of inputs involved in switching

This paper exploits useful skew to improve system performance and robustness. We formulate a robust integer linear programming problem considering the interactions between data and clock paths on a microprocessor chip to improve clock frequency. The timing slack is optimized for each path to determine a clock schedule. The percentage of timing violations, obtained from a 1000 point Monte Carlo simulation, is higlighted as yield predictions and conveys the robustness of the clock schedule. The results show performance improvement of up to 9.747% with 20% yield and up to 6.682% with 100% yield. The novelty of the proposed method is its ability to tradeoff between performance improvement in frequency and robustness, via a single variable in the formulation.

In this paper, a methodology for analyzing closed loop clock distribution and active deskewing networks is proposed. An active clock distribution and deskewing network is modelled as a closed loop feedback control system using state space equations. The state space models of the system were then used to simulate the clock deskewing scheme, and most importantly, to analyze the stability using the integral quadratic constraints method. Such a systematic analysis method can be very useful to designers as they will be able to determine how the deskewing network behaves, thus, avoiding repeated simulations. The proposed approach can be further extended to determine performance of such systems under different configurations. We show how the proposed method is applied to an experimental clock deskewing system for performance and stability analysis.

We propose a sensitivity-based method to allocate decoupling capacitors (decaps) incorporating leakage constraints and tighter data and clock interactions. The proposed approach attempts to allocate decaps not only based on the power grid integrity criteria, but also based on the impact of power grid noise on timing criticality and robustness. The resulting algorithm reduces the power grid noise to below a threshold and improves the performance or timing robustness of the circuit at the same time.

A formal methodology for the analysis of a closed loop clock distribution and active deskewing network is proposed. In this paper an active clock distribution and deskewing network is modeled as a closed loop feedback system using state space equations. State space analysis allows systematic analysis of any clock distribution and deskewing system to determine various conditions under which a system can overcompensate and become potentially unstable. Such an analysis can be very useful to designers as they will be able to determine analytically as to how the clock deskewing system behaves. By using the proposed approach, repeated simulations can be greatly limited and maybe entirely avoided. We applied the proposed method to an experimental clock deskewing system to illustrate the effectiveness of the proposed approach. The proposed approach can be further extended to determine performance of such systems under different configurations.

Performance optimization is a critical step in the design of integrated circuits. Rapid advances in very large scale integration (VLSI) technology have enabled shrinking feature sizes, wire widths, and wire spacings, making the effects of coupling capacitance more apparent. As signals switch faster, noise due to coupling between neighboring wires becomes more pronounced. Changing the relative signal arrival times (RSATs) alters the victim line delay due to the varying coupling noise on the victim line. The authors propose a sensitivity-based method to analyze delay uncertainties of coupled interconnects due to uncertain signal arrival times at its inputs. Compared to existing methods of analyzing delay uncertainties of coupled interconnects, the simulation results show that the proposed method strikes a good balance between model accuracy and complexity compared to the existing approaches.

This paper presents a new method of adapting body biasing on a chip during post-fabrication testing in order to mitigate the effects of process variations. Individual well biasing voltages can be changed to be connected either to a chip wide well bias or to a different bias voltage through a self-regulating mechanism, allowing biasing voltage adjustments on a per well basis. The scheme requires only one bias voltage distribution network, but allows for back biasing adjustments to more effectively mitigate die-to-die and within-die process variations. The biasing setting for each well is determined using a modified genetic algorithm. Our experimental results show that binning yields as low as 17% can be improved to greater than 90% after using the proposed IWABB method.

With continuing scaling of CMOS process, process variations in the form of die-to-die and within-die variations become significant which cause timing uncertainty. Statistical design methods have been proposed in the past to model the impact of process variations. However, all the existing methods deal almost exclusively with modeling delay variations of logical gates or physical variations of interconnect wires. This paper proposes a method of analytically analyzing statistical behavior of multiple coupled interconnects with an uncertain signal arrival time at each interconnect input (aggressors and the victim). The method utilizes delay-change characteristics due to changes in relative arrival time between an aggressor and the victim. The results show that the proposed method is able to accurately predict delay variations through a coupled interconnect.

We present single- and dual-rail mixed pass-transistor logic (PTL) synthesis method based on genetic search and compared the results with their conventional static CMOS counterparts synthesized using a commercial logic synthesis tool in terms of area, delay, and power in an experimental 0.1- and 0.13-/spl mu/m CMOS technologies as well as a 0.13-/spl mu/m floating-body partially depleted silicon-on-insulator (PDSOI) process. The proposed synthesis method first performs a search for possible matches between a logic structure and a set of predefined PTL/static logic gates using binary decision diagrams (BDDs). The unique contribution of our approach is the use of a genetic algorithm to determine the best mixture of PTL and static cells based on area and power. Our experimental results demonstrate that both single- and dual-rail mixed PTL circuits synthesized using the proposed mixed PTL/CMOS synthesis method outperforms their static counterparts in delay and power in bulk CMOS as well as silicon-on-insulator (SOI) CMOS technologies. The average power of single- and dual-rail mixed PTL/Static ISCAS'85 benchmark circuits using the proposed method in the 0.1-/spl mu/m bulk CMOS process are 73% and 50% better than their static counterparts with performance gains of 5% and 10%, respectively.

Matching input/output (I/O) driver output resistance to transmission line impedance is critical for high-speed I/O operation in source series termination environments. Tuning driver output resistance can be accomplished through the use of calibration circuitry. Under ideal conditions, calibration circuitry can properly calibrate an I/O driver. Operating in an environment with die process, voltage, and temperature variations, that same calibration circuitry may perform improperly. This brief presents an I/O driver design that is less sensitive to process, voltage, and temperature variations. The proposed driver design provides a near linear or flat, output resistance response verses output voltage. Advantages of the proposed I/O driver architecture lie in applications where the output DC operating point may have a large variation, thus, reducing the error in matching output resistance.

Reliable packages for modern chips are crucial for satisfactory system performance. In order to ascertain package's performance, an equivalent electrical model is plugged into circuit simulations and the package's performance characteristics can be analyzed. However, one implicit assumption designers make is that these equivalent electrical models are accurate for performance characterization of packages. For modern high-speed designs, verification of the accuracy of these models is imperative and can only be carried out on real-silicon. In addition, signal integrity for inter-chip communication is crucial from a systems perspective. To study the signal integrity of data under different PVT (process variation, voltage, and temperature) conditions, appropriate test structures are needed. Data can be subjected to controlled variations through these structures and its integrity can be studied. And finally, testing package reliability at high temperatures is important since on-chip temperatures are increasing dramatically as processes continue to scale. The test chip presented in this design is intended to allow 1) circuit and package designers to evaluate and validate the accuracy of package models under a variety of environment conditions; 2) system designers to evaluate package/system level signal integrity issue before actual chips are available; and 3) system designers to evaluate on-chip temperatures and to study thermal integrity of packages. The test chip includes a variety of features to achieve these goals. The test chip is fabricated at TSMC in a 0.18 μm CMOS process. The measurement results and the die microphotograph will be sent later as soon as they are available. This paper presents the layout based simulation results.

Object-based coding and description in real time are increasingly important for many image and video applications. We propose a very large scale integration (VLSI) architecture based on a novel segmentation algorithm for extracting objects in video. The segmentation architecture of a frame mainly consists of two functional phases. In the first phase, pixel-based static and dynamic features in video are extracted, filtered, normalized. These multiple features are labeled using a self-organizing feature map neural networks architecture to generate initial segmentation labels. An edge fusion module in the second phase combines the initial segmentation labels and a linked edge map of a frame to generate more accurate segmentation where region boundaries are closer to the actual object boundaries. Computational and hardware complexities of the proposed architecture are estimated in terms of the number of clocks, arithmetic components, gates, and memory requirements. The performance of the proposed VLSI architecture demonstrates the possibility of performing object-oriented video segmentation in real time.

We present the impact of technology scaling on mixed PTL/static circuits and compare the results with that of domino and conventional static CMOS. The state-of-the-art technologies of 0.18 /spl mu/m, 0.13 /spl mu/m, and 0.1 /spl mu/m were used in the study with V/sub dd/ being scaled accordingly. The benchmark suite consists of 10 circuits of varying complexities and they are actual circuits used in a state-of-the-art 64-bit microprocessor in the form of either dynamic or static CMOS circuits. The objective of this work is to determine how performance and power consumption scales with technology scaling. Our experimental results show that the mixed PTL/static circuit style is a promising alternative in power and power-delay product while achieving comparable delay to the dynamic circuit style.

It has been well recognized that the impact of on-chip inductance on some critical nets, such as clock nets, is significant and can not be ignored in delay modeling for these nets. However the impact of on-chip inductance on signal nets in general is still not well understood. We present results of analyzing inductive effects on signal nets for ultra-deep submicron technologies. The analysis is based on a Al-based 0.18 /spl mu/m CMOS process and a Cu-based 0.13 /spl mu/m CMOS process. The impact of on-chip inductance is shown to be insignificant if we assume a perfect power supply network around the interconnect routes. Otherwise, the impact of on-chip inductance can be significant. Furthermore, the results presented in this paper illustrate the impact of on-chip inductance one would expect from transitioning from an Al-based interconnect technology to a Cu-based interconnect technology.

In order to improve the efficiency of behavioral model verification, it is important to determine the points of diminishing return for a given verification strategy. This paper compares the existing stopping rules and presents a new stopping rule based on static Bayesian technique. The new stopping rule was applied to verifying 14 complex VHDL models. We used the figure of merit to compare the efficiency of the stopping rules. The results in terms of coverage and verification time were shown to consistently outperform existing stopping rules.

We propose an accurate measure of channel routing density and its application to global routing. Our congestion metric calculation method considers the wire scenarios in a channel.

We present a segmentation technique for image sequences using self organizing feature maps (SOFM). Our goal is to develop a method which can identify homogeneous regions in a frame to represent higher level objects for content based manipulation of image sequences. The proposed scheme extracts pixel based multiple features, such as motion and textures, and then, different weights are applied to each feature component based on motion confidence measures. These multiple feature spaces are transformed to one dimensional label space by using the SOFM. The oversegmentation neural network outputs are merged in order to generate desired segmentation resolution. Our experimental results show the validity of the proposed scheme.

This paper describes the defect coverage evaluation of memory testing algorithms. Realistic CMOS defects were extracted from a 2/spl times/2 SRAM layout using an IFA tool, and circuit simulations were performed to measure the defect coverages of the eleven memory testing algorithms.

This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with three parameters, which include the fault coverage upper bound, UB, the fault coverage lower bound, LB, and the rate of fault coverage change, /spl alpha/. The fault coverages using three different testing scenarios, which are no DFT, scan, iddq testing, are predicted using circuit design information, such as gate count, I/O count, and FF count. These parameters are often readily available at the early stage of VLSI design. Finally, the composite fault coverage is estimated by combining different fault coverages. Experimental result showed a 1.9% model estimation error with a given circuit information in the early design.

A real-time algorithm and its VLSI implementation for edge linking is presented. The linking process is based on the break points' directions and the weak level points. The proposed VLSI architecture is capable of outputting one pixel of the linked edge map per clock cycle with a latency of 11n+12 clock cycles, where n is the number of pixel columns in the image.

The manufacturing of high-quality and reliable semiconductor memories is very important. Many memory testing algorithms have been proposed to improve the quality of semiconductor memories by screening out different memory functional faults. However, the relationships between memory function fault types and the types of defects which cause the functional faults are not well understood. Therefore, the effectiveness of memory testing algorithms based on the functional fault models cannot be realistically determined. This paper evaluates the effectiveness of the memory testing algorithms based on the defect coverage by comparing the defect coverage of known memory testing algorithms and the functional fault coverage of the same testing algorithms using the same defect statistics. The experimental results show that the differences among the defect coverage of the 11 memory testing algorithms other than checkerboard and sliding diagonal tests were not significant as previously believed using memory functional fault coverage as the coverage metric.

This paper presents an optimized column fast Fourier transform (FFT) architecture, which utilizes bit-serial arithmetic and dynamic reconfiguration to achieve a complete overlap between computation and communication. As a result, for a clock rate of 40 MHz, the system can compute a 24-b precision 1K point complex FFT transform in 9.2 /spl mu/s, far surpassing the performance of any existing FFT systems.

We present a high performance edge detection architecture for real-time image processing applications. The architecture is finely pipelined. The proposed ASIC is capable of producing one edge-pixel every clock cycle. At a clock rate of 10 MHz, the architecture can process 30 frames per second, where the size of each frame is 640/spl times/480 8-bit pixels. The ASIC was laid out and fabricated using Samsung's 0.8 /spl mu/m double-metal CMOS process.

This paper proposes a rest cost prediction model which estimates the cost of lC testing in a manufacturing environment. The model predicts chip testing cost and quality of test using a set of circuit manufacturing parameters. The objective is to use these circuit parameters which are available at the early stage of the design cycle to determine and optimize manufacturing test cost.

This paper describes an ASIC yield model based on the CMOS bridge fault model. The model predicts defect sensitive area early in the design cycle as a function of number of gates and nets.

Soft errors resulted from alpha-particle strikes are one of the major factors that reduces the reliability of memory chips. One way to improve reliability of the memory chip is to employ an on-chip code (ECC). This paper presents a triple-error correcting and quadruple-error detecting (TEC-QED) code that is capable of correcting three and detecting four soft errors simultaneously. Its design is based on odd-weight-column SEC-DED code in conjunction with the parity technique. Results show that timing overhead of less than 10 ns can be expected. The proposed code improves the mean time between failure (MTBF) by a factor of 250% when compared to DEC-DED APC and by a factor of 1300% when compared to any SEC code.>

This paper presents an optimized column FFT architecture which utilizes bit-serial arithmetic and dynamic reconfiguration to achieve a complete overlap between computation and communication. As a result, the system can compute a 24-bit precision 1 K point complex FFT transform within 9.25 /spl mu/s, far surpassing the performance of any existing FFT systems.>

An analysis of the main contributors to the quality and cost of complex board manufacturing is presented. Manufacturing data from three boards built at Hewlett-Packard and simulation models are used to derive the sensitivity of quality and cost versus Surface Mount Technology (SMT) solder defect rate component functional defect rate and test coverage. A new yield model which accounts for the clustering of solder defects is introduced and a first order estimation of the cost of implementing the IEEE 1149.1 standard on ASICs is given.

A board and multi-chip module (MCM) manufacturing test simulator (MTSIM) is described, MTSIM is a concurrent engineering tool used to simulate the manufacturing test and repair aspects of boards and MCMs from design concept through manufacturing release. MTSIM helps designers select assembly process, specify, design for test (DFT) features, select board test coverage specify ASIC defect level goals, establish product feasibility, and predict manufacturing quality and cost goals. MTSIM was implemented in the Mentor Graphics Falcon framework at Colorado State University (CSU) and validated with high performance assemblies at Hewlett-Packard (HP). MTSIM is a step towards the simulation of the whole board/MCM assembly factory.

A memory architecture with the capability of self-testing and self-repairing is presented. The contributions of this memory architecture are twofold. First, because it incorporates self-testing and self-repairing structures, the memory chip can perform tests, locate faults, and repair itself without any external assistance from either test engineers or test equipment. This will greatly improve the functional yield and reduce the production cost. Second, the hierarchical organization used to achieve optimal conditions for memory access time also helps increase the efficiency of the self-testing and self-repairing structures.>

A memory architecture with the capability of self-test and self-repair is presented. The contributions of this memory architecture are twofold. First, it incorporates self-testing and self-repairing structures in the memory. As a result, the memory chips can perform tests, locate faults, and repair themselves without any external assistance, greatly improving the functional yield and reducing the production cost. Second, the architecture uses a hierarchical organization to achieve optimal conditions for memory access time. The hierarchical organization also increases the efficiency of the self-testing and self-repairing structures.>

This paper presents a self-testing and self-repairing strategy for ultra-high capacity memories. The self-testing and self-repairing structure allows ultralarge scale memory chips to perform tests, locate faults, and repair itself without any external assistance from either test engineers or test equipment. This will drastically improve the functional yield and reduce the production cost. The efficiency of self-testing and self-repairing strategy is supported by a hierarchical memory organization.