A fast-locking phase-locked loop (PLL) with a joint phase and frequency compensation technique is presented. With the proposed maximum phase error detector (MPED), the accumulated phase error can be well compensated right after frequency acquisition to improve the settling time of the PLL. The proposed PLL operating at a 0.9-V supply power was fabricated using a 28-nm CMOS process. The total settling time can be improved by 78% with a 200-ppm settling accuracy. The output frequency of the PLL is operated at 10GHz with a power consumption of 2.76mW.

This paper presents a 1 GS/s, 10-bit pipelined-SAR ADC with a proposed two-stage amplifier that no need frequency compensation. The proposed amplifier mimics the three-stage ring amplifiers. With the transmission gates adopted in the first stage, the voltage drop creates a dead-zone that biases the output stage in the subthreshold region, providing stability. Fabricated in a TSMC 28-nm technology, the proposed ADC achieves a SNDR of 52.01 dB under 1 GS/s sampling rate, while consuming only 7.99 mW.

This work presents a 5-GHz frequency-modulated continuous wave signal generator (FMCW). The presented circuit aims to generate a wider frequency modulation bandwidth at low center frequency that grants significant advantage at saving power. Utilizing a fractional- N phase-locked loop (PLL)-based synthesizer with a 50-MHz reference frequency as the FMCW generator, the synthesizer modulates the carrier frequency across a range of 700 MHz. A Type-3 architecture with a switchable polarity is embedded to improve the linearity around the chirp turning-around points (TAPs) and switching-band points (SBPs). Switching Band Control (SBC) circuit and Multi-varactor LC Voltage Control Oscillator (MV-VCO) are proposed as an efficient method to increase the modulation range so that the FMCW signal generator can achieve 21.43-cm resolution in distance detecting. Fabricated in a TSMC 40-nm 1P10M CMOS technology, the proposed generator consumes 3.3 mW power and occupies 0.497mm2die area. The measured root-mean-square (rms) frequency error of the generated triangle chirp over 1.15ms period is 625kHz.

This paper presents a router, which tackles a classic algorithm problem in EDA, obstacle-avoiding rectilinear Steiner minimum tree (OARSMT), with the help of an agent trained by our proposed policy-based reinforcement-learning (RL) framework. The job of the policy agent is to select an optimal set of Steiner points that can lead to an optimal OARSMT based on a given layout. Our RL framework can iteratively upgrade the policy agent by applying Monte-Carlo tree search to explore and evaluate various choices of Steiner points on various unseen layouts. As a result, our policy agent can be viewed as a self-designed OARSMT algorithm that can iteratively evolves by itself. The initial version of the agent is a sequential one, which selects one Steiner point at a time. Based on the sequential agent, a concurrent agent can then be derived to predict all required Steiner points with only one model inference. The overall training time can be further reduced by applying geometrically symmetric samples for training. The experimental results on single-layer 15x15 and 30x30 layouts demonstrate that our trained concurrent agent can outperform a state-of-the-art OARSMT router on both wire length and runtime.

Cell layout synthesis is a critical stage in modern digital IC design. In previous automatic synthesis solutions, algorithms always consider only cell area and routability. This is the first work to propose a method of delay-aware transistor placement for cell library synthesis at the sign-off level. We consider the delay and area of a cell in the transistor placement stage. Our methodology consists of three major steps. First, a search tree finds the candidate placement list that has the smallest area in a large search space. Then, a neural network filters out the unroutable candidates. Finally, a comparative convolutional neural network model, trained by sign-off level data, sorts the delays during the early placement stage. The experimental results show that the proposed CNN-based routable classifier can achieve up to 98% accuracy, and the proposed CNN-based delay ranker also can achieve up to 94.6% accuracy. The work obtains a 1.77% average sequential component delay improvement over the traditional cell synthesis method. Our method also has a 0.97% better delay performance than the human-level design.

A 5 GHz outer-loop phase noise filter (PNF) circuit is proposed to suppress phase noise. By using an active delay line (DL) and sampling circuits to perform the delay-sampling (DS) technique, one can further reduce the phase noise at the selected offset frequency with no need of the reference clock signal. With a 50-ns DL, the PNF circuit achieves 10-dB phase noise reduction at around a 5-MHz offset frequency. This PNF was fabricated in a 40-nm CMOS technology while the core circuit area occupies 0.012 mm2with 2.97 mW power consumption.

Satisfying timing requirements is the most challenging phase of the modern complex system-on-chip (SOC) design. The timing closure of the static timing analysis (STA) is a necessary but time-consuming stage before tapeout. Physical design tools are normally ineffective in obtaining accurate timing estimates, so the accurate timing calculation must be conducted in the signoff level timer after each physical modification on designs. This paper proposes a way to reduce the number of iterations between the signoff timer and the physical implementation procedures. Approximate timing models for extracting the signoff timer information and the nonlinear library are used in the optimization of the timing-driven placement (TDP). The accurate estimation of net and cell delays is integrated into TDP, so the optimal positions of cell movement can be obtained. This post optimization algorithm was entered into the benchmark of the ICCAD15 incremental timing-driven contest, and the embodiments were obtained from the top three teams. Under the same design constraints, the proposed method yielded significant improvements in all kinds of default design chip.

A ΔΣ modulator with dual-VCO-based quantizers is proposed to enhance SFDR of the converter. To alleviate the nonlinear VCO voltage-to-frequency tuning characteristics, a shifted-averaging dual VCO architecture is proposed. Furthermore, a VCO which merges a voltage summer and a current DAC for excess loop delay compensation is designed, drastically reducing the complexity of the circuit. The measured results of the proposed modulator implemented in a 65-nm CMOS technology demonstrates a peak SNDR of 65.2 dB and a peak SFDR of 75.4 dB at 21.1-mW power, with a 20-MHz bandwidth.

A 2.4-GHz high-efficiency adaptive rectifier with extended input power range is presented. The rectifier consists of two differential-type sub-rectifiers and a control circuit. The proposed control circuit can detect the input power level by sensing the converted output voltage of the rectifier and then generating two control signals to switch the rectifier between two operation modes. This device has been fabricated in 0.18- μm CMOS technology. With two three-stage differential-type rectifiers as the sub-rectifiers, the optimal power conversion efficiency (PCE) region is extended to 11 dB by the proposed technique under a 2- kΩ load. Moreover, the proposed rectifier has two peak PCEs, which are 47% and 41% at input powers of 8.9 and 2.1 dBm, respectively.