This paper presents an intellectual property (IP)-based system-on-chip (SoC) synthesis framework focusing on how to select IPs from different sources and how to integrate the selected IPs using on-chip buses. In order to synthesize an on-chip bus-based SoC architecture using IPs with imprecise design costs, we propose a possibilistic mixed integer linear programming (PMILP) model, which is converted into an equivalent mixed integer linear programming (MILP) model without increasing the computational complexity. Then, the equivalent MILP model is solved to decide whether each IP is selected or not, and to locate the selected IP on the optimal on-chip bus of a hierarchical bus architecture that consists of on-chip buses with different bus attributes. Experimental results on an MP3 decoding system show that the IP-centric design space with uncertainty can be successfully explored using the proposed scheme.

This paper describes the MetaCore system which is an application-specific instruction-set processor (ASIP) development system targeted for digital signal processor (DSP) applications. The goal of the MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost, and design turnaround time. The MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and structural/behavioral specifications for the target processor and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration and instruction set are chosen, the system helps generate the target processor design in the form of hardware description language (HDL) along with the application program development tools such as C compiler, assembler, and instruction set simulator. The effectiveness of the MetaCore system was verified with a successful design of MDSP-II, a programmable DSP processor targeted for mobile communication.

This paper describes the MetaCore system which is an ASIP (Application-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost and design turnaround time.