This paper presents a 12-bit, 700-MS/s pipeline ADC fabricated in TSMC 40-nm technology, with a focus on power optimization in residue amplifiers and comparator cells. The effective transconductance of the inter-stage amplifiers and comparators is optimized for the minimum power consumption while meeting CDAC matching requirements. The architecture consists of two 3.5-bit/stage blocks in cascade with a sub-range 6-bits flash ADC. A two-stage class AB residue amplifier with cascode output stage and complementary differential pairs is employed, effectively double its DC gain and capable of achieving twice the slew rate (SR) and gain-bandwidth product (GBW) compared to the conventional design with equivalent power consumption. The residue amplifier does not require specific frequency compensation since the cascode output stage and large load capacitor determine the dominant pole that is naturally separated from the pole generated at the output of the first stage. To further enhance ADC’s power efficiency, the multiplying digital-to-analog converter (MDAC) of the second stage is designed to enable the functionality of the subsequent sub-range 6-bit flash ADC. The two-step 6-bit backend stage resolves the last 3 MSBs and 3 LSBs sequentially, significantly reducing power consumption. A digital calibration scheme employing key DC test signals effectively correct gain and non-linearity errors. Experimental results for a 40nm CMOS prototype show that the proposed pipeline ADC achieves a Signal-to-Noise and Distortion Ratio (SNDR) of 69.2 dB and a Spurious-Free Dynamic Range (SFDR) of 81.5 dB at low input frequencies. 68.5 dB SNDR and 80.7 dB SFDR near the Nyquist frequency at 700 MS/s are achieved. The ADC core occupies an active area of$0.56~mm^{2}$and consumes 24.3 mW from a 1.2 V power supply. Near Nyquist frequency, the measured Schreier figure of merit is approximately 170.1 dB.

This article presents a 130-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) architecture that uses a 9-bit capacitive DAC (CDAC) and innovative techniques that include passive amplification circuitry without engaging active components and the strategic connection of a unity capacitor to multiple reference voltages, to achieve a total of 12 bits. The proposed passive amplification technique saves 27% of the ADC area through reducing the CDAC size by 50% compared to a conventional 10-bit CDAC +2-bit voltage reference design for a 12-bit resolution. Compared with the conventional 12-bit C-DAC SAR, the proposed SAR-ADC saves over 75% of the active area. The measurement results reveal that the core of the proposed ADC architecture dissipates 3 mW. Fabricated in a mainstream 40-nm CMOS technology, the proposed ADC attains SNDR/SFDR ratios as high as 63.5/72.13 dB for a 10-MHz sinusoidal test tone; the SAR active area is about$0.00966~\text {mm}^{2}$. Furthermore, this architecture yields favorable results regarding the Walden figure-of-merit of approximately 26.5 fJ/conv-step while maintaining Schreier FOM around 165.37 dB when measured at 10 MHz.

This paper proposes a fractional spur cancellation technique designed for fractional-N frequency synthesizers. A time domain quantitative analysis is conducted to provide an intuitive understanding of the origin of fractional spurs and to formulate the relationship between the phase error of the feedback signal and the division factor of the frequency divider. By utilizing a dual loop charge-pump based architecture that generates two feedback phases, one leading and one lagging the reference phase, the two loops effectively clamp the reference phase between the two feedback phases and inject complementary charge components to achieve spur reduction. Unlike conventional methods, the proposed analog spur cancellation technique eliminates the need for additional signal processing stages within the loop. This offers several advantages, including reduced complexity, no introduction of additional distortion sources, and minimal impact on loop dynamics. Simulation results employing TSMC 40nm technology demonstrate that the proposed technique can achieve a worst-case fractional spur level of -96.6dBc in a charge-pump based fractional-N frequency synthesizer, offering moderate immunity to mismatches while also slightly improving the phase acquisition time and jitter performance.

A foreground matrix-based digital calibration technique is proposed for high-performance Nyquist analog-to-digital converters (ADCs) to reduce the performance loss due to transistor limitations and unavoidable converter component mismatches. A set of patterns is obtained during foreground calibration and then used during normal operation to correct the ADC output using conventional digital circuitry. This technique is validated through a 12-bit SAR ADC running at 350 MS/s and a test sinusoidal tone at 10 MHz that can be efficiently generated on-chip. The simulation results of the ADC including 2% random capacitive DAC (CDAC) array elements mismatch, employing the proposed calibration methods show 16.4/14.6 dB signal to distortion ratio (SNDR)/ spurious free dynamic range (SFDR) improvement, respectively. Besides, a significant improvement in both differential non-linearity (DNL) and integral non-linearity (INL). The proposed calibration technique is adopted to calibrate a fabricated 13-bit Pipeline ADC that operates at 260 MS/s, which achieves 68.23 dB and 85.82 dB SNDR/SFDR for low frequencies. When measured at 123.129 MHz, the ADC achieves 65.9/80 dB SNDR/SFDR, respectively. The chip was manufactured in TSMC 40-nm CMOS process.

Teaching analog circuits courses in the current digital era is a significant challenge for instructors. The mathematics needed for the first course on electronics is basic and the analyses are not complicated either. However, it typically requires conceptual understanding and intuition that has to be conveyed in order to avoid frustration during the assembly and testing of amplifiers in the lab, especially when students design them from scratch. A number of excellent textbooks are available that cover the theory, but it is difficult to find compelling literature that extends this knowledge to practical applications. In this paper, basic amplifier theory is revisited and with attention to considerations related to non-idealities and variations. The concept of sensitivity and its use is emphasized as well as, using the benefits of source/emitter degeneration as an example. It is shown that this degeneration indeed corresponds to an effective negative feedback mechanism that improves linearity and accuracy in addition to increasing the amplifier input impedance, all at the expense of reduced voltage gain.

In this paper, an interference-tolerant three-level synchronization scheme for wireless communication systems based on Direct Sequence Spread Spectrum (DSSS) is presented. Although the proposed synchronization scheme is demonstrated in a mixed signal IC solution, it is exportable to fully digital realizations. The proposed technique synchronizes the received pseudo-random sequence (PRS) modulated signal with the receiver (RX) reference PRS by making use of its autocorrelation properties. The proposed scheme employs 3 levels that make the proposed scheme tolerant to strong in-band interferences. Experimental results for the prototype demonstrate the capabilities of the proposed approach to achieve over 50% of clock cycle tracking even in the presence of interferences with a power of 5dB higher than the desired signal power. Fabricated in a mainstream 40nm CMOS technology, the synchronization scheme employs 100MHz PRS at TX and RX; the proposed solution consumes 18.7mW power and around 0.087mm2silicon area.

A highly-linear I-channel receiver prototype is presented for a 3 to 6 GHz broadband radio system with a 200 MHz baseband bandwidth and verified to operate under congested spectrum environments. A direct conversion receiver developed from this prototype is suitable for a cognitive radio, fifth-generation (5G) receiver, and other wireless systems with a total (in-band signal plus blocker) power above -6.0 dBm. The broadband receiver consists of a low-noise transconductance amplifier, a passive mixer, a wideband transimpedance amplifier and a power-efficient minimally-invasive baseband filter. The low-noise transconductance amplifier with high linearity employs a cross-coupled structure and resistive degeneration to achieve low noise and high linearity simultaneously. The common-gate based LNTA achieves 2.3 dB noise figure in simulation. Fabricated in a mainstream 40 nm CMOS technology, the worst-case measured system noise figure is under 5.8 dB at 3 MHz baseband frequency, and the conversion gain is larger than 12.8 dB with passband variations under 2 dB from 1 MHz up to 200 MHz signal bandwidth. Over 3 to 6 GHz, the receiver's in-band IIP3 and input P1db are higher than 15.1 dBm and 3.0 dBm, respectively, whereas the power consumption varies from 64.1 mW to 69.6 mW.

This paper presents a continuous-time multistage noise-shaping (MASH) delta-sigma modulator (CT-AΣM) employing finite impulse response (FIR) digital-to-analog converters (DACs) and encoder-embedded loop-unrolling (EELU) quantizers. The proposed MASH 1-1-1 topology is a cascade of three single-loop first-order CT-AΣM stages, each of which consists of an active RC integrator, a current-steering DAC, and an EELU quantizer. An FIR filter in the main 1.5-bit DAC improves the modulator's jitter sensitivity performance. FIR's effect on the noise transfer function of the modulator is compensated in the digital domain, thanks to the MASH topology. Instead of employing a conventional analog direct feedback path for excess loop delay compensation, a 1.5-bit EELU quantizer based on multiplexing comparator outputs is proposed; this approach is suitable for high-speed operation. Fabricated in a 40-nm lowpower CMOS technology, the modulator's prototype achieves a 67.3 dB of signal-to-noise-and-distortion ratio, 68 dB of signalto-noise ratio, and 68.2 dB of dynamic range within 50.5 MHz of bandwidth, while consuming 19 mW of total power.

A 13bit 200MS/s pipeline ADC with current-mode MDAC is implemented in this work. Compared with a conventional MDAC architecture, the proposed current mode MDAC reduces power consumption for the residual amplifier between two pipelined stages. The fabricated ADC achieves a 58.4dB / 57.6dB SNDR and a 75dB / 72dB SFDR for a sinusoidal input at 4.15MHz / 97.9MHz respectively. The power consumption of the ADC operating at 200MS/s is 8.4mW and the conversion FoM is 64fJ/conv-step. The prototype occupies an active area of 0.23mm2 in a 40nm CMOS technology.

A low-power 2-16 GHz frequency synthesizer fabricated in 130nm CMOS technology is presented. A singlesideband mixer combines feed-forward and regenerative mixing techniques as well as frequency divide-by-two circuits to achieve the wide frequency range. A dynamic current-clipped QVCO that exhibits excellent phase noise and outstanding quadrature phase accuracy is developed. The frequency synthesizer fabricated in 130nm CMOS technology achieves 0.6ps jitter and spurs tones under -42dBc while consuming a maximum power of 64mW with 1.2/1.8V power supplies.

Design techniques to provide robustness against loop saturation due to blockers in ΣA modulators are presented. Loop overload detection and correction are employed to improve the analog-to-digital converters (ADCs) tolerance to strong blockers; a fast overload detector activates the input attenuator, maintaining the ADC in linear operation. To further improve ADCs blocker tolerance, a minimally invasive integrated low-pass filter that reduces the most critical adjacent/alternate channel blockers is implemented. Measurement results show that the proposed ADC implemented in a 90nm CMOS process achieves 69dB dynamic range over a 20MHz bandwidth with a sampling frequency of 500 MHz and 17.1 mW of power consumption. The alternate channel blocker tolerance at the most critical frequency is as high as -5.5 dBFS while the conventional feedforward modulator becomes unstable at -23.5 dBFS of blocker power. The proposed blocker rejection techniques are minimally invasive and take less than 0.3 μs to settle after a strong agile blocker appears.

A process-variation resilient current mode logic (CML) is presented. The proposed CML employs time-reference-based adaptive biasing chain with replica load to address performance degradation over the process variations. It adjusts variable load resistor to simultaneously regulate time constant, voltage swing, level shifting, and DC gain. The prototype demonstrates the process-variation resiliency of the proposed solution by showing performance degradation over the process corners. Over 20% of polygate resistance variation, the proposed CML suppresses the degradation of speed and rms jitter less than 4.3% and 0.15 ps while conventional CML results in 13% and 3.8-ps degradation, respectively.

A 3-bit current-mode flash quantizer with current summing stage in a commercial 90-nm CMOS technology is presented. The topology is intended for low-power feed-forward continuous-time sigma-delta modulators. Current summation is realized using a common-gate structure. Replicas of the input signal current are compared with the reference currents through high-impedance nodes that ease the signal quantization. The comparison stage employs reset switches to enable fast comparisons. The proposed approach involves zero crossing comparators, and it employs current references instead of voltage references that demand a power-hungry resistive ladder. Results show that the proposed current-mode approach is faster than the conventional voltage-mode flash approach, and it requires a smaller input capacitance while consuming 53% less power. A 3-bit prototype design has a measured effective number of bits over 2.6 bits up to 2-GHz clock frequency with 10-MHz full-scale input signal. At 1.48-GHz clock frequency, the static differential nonlinearity (DNL) and integral nonlinearity (INL) errors are within -0.206 least significant bit (LSB) and 0.206 LSB, respectively. The proposed current-mode flash analog-to-digital converter (ADC) core dissipates 3.34-mW analog power from a 1.2 V supply while operating at 1.48 GHz. The core area of the ADC including the biasing circuitry is 0.0276 mm2.

A current-mode flash analog-to-digital converter (ADC) with current summing stage was designed and evaluated. The topology is intended for low-power feed-forward continuous-time sigma delta (CTSD) modulators and was fabricated in a commercial 90nm CMOS technology. A 3-bit prototype has an effective number of bits (ENOB) of 2.87 bits at 2GS/s with 12MHz full-range input power. The static DNL and INL errors are both in the range of 0.24 LSB. The ADC achieves an SNDR of 15dB with a 1GHz input signal and an SNDR above 19dB for input signals below 300MHz. A major advantage of this architecture is its voltage scalability as well as the reduced input capacitance. The proposed ADC core dissipates 3.1mW power from a 1.2V supply while operating at 2GHz.

VLSI circuits of the 45-nm technology and beyond are increasingly affected by process variations as well as aging effects. Overcoming the variations inevitably requires additional power expense, which in turn aggravates the power and heat problem. Adaptive supply voltage (ASV) is an arguably power-efficient approach for variation resilience since it attempts to allocate power resources only to where the negative effect of variations is strong. We propose a dual-level ASV (dual-ASV) system for designs containing many timing critical paths. This system can simultaneously provide ASV at both coarse-grained and fine-grained levels, and has limited power routing overhead. The dual-ASV system is compared with conventional ASV through SPICE simulations on benchmark circuits. The results indicate that the dual-ASV system consumes significantly less power and achieves similar performance in the presence of variations.

An integrated ultrahigh-frequency (UHF) receiver is presented. A systematic analysis to quantify the interdependence of baseband filter and analog-to-digital converter (ADC) dynamic range in broadband receivers is presented. This analysis shows that: (1) low-order Butterworth filters are favorable when undesired power is dominated by far out blockers and (2) high-order inverse Chebyshev filters can reduce the resolution of a subsequent ADC by up to two additional bits in the presence of adjacent analog narrowband blockers. Based on the analysis, a cascaded, programmable, hybrid active-RC and switched-capacitor (SC) baseband filter is proposed. An all-digital nonoverlap clock tuning system to minimize the variation of available settling time window in SC circuits is also proposed. The receiver integrates the proposed filter with an RF variable gain amplifier (RFVGA) and a passive mixer. This receiver achieves a measured noise figure of 7.9 dB, an IIP3 of -8 dBm at maximum gain and +2 dBm at 9-dB RF attenuation. The chip consumes 120 mW (RFVGA, mixer and I-channel baseband) from 1.8-V analog/2.5-V digital dual supply and occupies 2.14 mm2in IBM 0.18-μm RF CMOS technology.

This paper presents a voltage-mode high speed driver to transmit serial AER data in scalable multi-chip AER systems. To take advantage of the asynchronous nature of AER (Address Event Representation) streams, this implementation al- lows an energy efficient burst-mode operation. This is achieved by switching on/off the driver in data pauses to reduce static power consumption. Impedance matching is calibrated continuously to track temperature variations, obtaining an optimal performance without degrading the data rate. Power management techniques for switching drivers are discussed and an internally compensated high speed regulator is presented. The system has been designed in a 0.35μm CMOS technology to transmit data rates up to 500Mbps using Manchester enconding. Layout extracted simulation results are presented, which include all interconnect parasitics. Estimated peak rate is 15Meps for 32 bit events. Simulated power consumption of transmitter and receiver at peak rate is 33.2mW, while below 100 Keps is 1.3mW.

This work presents an integrated ultra high frequency (UHF), broadband direct-conversion receiver. The receiver integrates a single-ended RFVGA, an on-chip single-to-differential balun, a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. Targeted to operate between 470-862 MHz, the receiver achieves a noise figure of 7.9dB, an IIP3 of -8dBm at maximum gain and an IIP3 of +2dBm at 9dB RF attenuation. The gain- and frequency-programmable baseband section implements an 8thorder inverse chebyshev low pass approximation achieving >42dB attenuation at an offset of 1.75 MHz for the 4 MHz frequency setting. Overall, the receiver consumes 120mW from 1.8V analog/2.5V digital dual supply and occupies 2.14mm2in IBM 0.18μm RFCMOS technology.

This poster shows how to efficiently observe high-frequency figures of merit in RF circuits by measuring DC temperature with CMOS-compatible built-in sensors.

A CMOS RF RMS detector is introduced. It generates a DC proportional to the RMS voltage amplitude of an RF signal. Its high input impedance and small silicon area make it suitable for the built-in testing (BIT) of critical RF blocks of a transceiver such as a low noise amplifier (LNA) and power amplifier (PA) without affecting their performance and with minimum area overhead. The use of this structure in the fault detection and diagnosis of a wireless transceiver is described and illustrated with an example. The transistor-level implementation of the proposed circuit is discussed in detail. Post-layout simulation results using CMOS 0.35/spl mu/m technology show that this testing device is able to perform an RF to DC conversion at 2.4GHz in a dynamic range of 20dB using an area of only 0.0135mm/sup 2/ and presenting an equivalent input capacitance of 22.5fF.

A compact system for the on-chip transfer function characterization of an analog circuit is presented. It consists of a phase and amplitude detector and a signal generator. A general methodology for the use of this structure in the functional verification of a circuit under test (CUT) is provided. An integrated implementation of the proposed system in CMOS 0.35 /spl mu/m technology is described along with circuit-level design considerations. Experimental results of the application of this system in the characterization of a commercial programmable gain amplifier for frequencies up to 160 MHz are also presented.

A compact and fully programmable Gaussian function circuit with temperature compensation is introduced. The programmability of the Gaussian circuit generator is carried out by using current sources. Hspice simulations for the proposed structure have shown deviations from the ideal Gaussian function below 3%. Breadboard results for the Gaussian circuit generator, in good agreement with the theoretical ones, are reported.

A family of CMOS Operational Transconductance Amplifiers (OTA's) have been designed for very small G/sub M/'s (of the order of nA/V) in the moderate inversion region of operation using several design schemes such as current division, floating gate input stages and bulk driven techniques. A detailed comparison has also been made among these schemes in terms of performance characteristics such as power consumption, active silicon area and signal to noise ratio (SNR). The design has been sent for fabrication in a 1.2 /spl mu/m n-well CMOS process with a power supply of 2.7 V.

In this paper a CMOS preamplifier for capacitive sources is presented. The 20 dB gain preamplifier achieves a dynamic range of 54 dB while the total harmonic distortion is below -50 dB. Monte Carlo analyses have shown output random offset voltages below 40 mvolts. The power consumption of the proposed preamplifier is 24 /spl mu/watts. All this has been achieved due to the use of a novel resistor and linearized OTAs.

This paper deals with the effect of the transistor mismatches on the performance of Fully Differential Operational Transconductance Amplifiers (FDOTA). A simple macro model including transistor mismatches is proposed. From this model, the four transfer functions that determine the behavior of the FDOTA can be easily obtained. These transfer functions are further discussed and some clues in the design of high-performance FDOTAs are provided. Experimental results for a 6 /spl mu/A/V FDOTA fabricated in a 1.2 /spl mu/m CMOS process are in good agreement with the theoretical and simulated ones.>

A switched-capacitor filter with independent programmable gain at either low frequency, passband frequency and high frequency band is presented. The gain at each of these frequency bands is controlled by a capacitor bank. This universal second order switched-capacitor filter employs 3 operational amplifiers, 3 capacitor banks and some additional capacitors. Experimental results, from a breadboard, are in good agreement with the simulated and theoretical ones.>