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L. Tissa Samaratunga

dblp:74/1990 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 50% Interconnection networks and networks-on-chip · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › network topology
hierarchical interconnection network		 0.011994
Memory Bandwidth Analysis of Hierarchical Multiprocessors using Model Decomposition and Steady-State Flow Analysis · IEEE Trans. Parallel Distributed Syst. 1994
Performance modeling and evaluation › performance model construction › memory system performance modeling
memory bandwidth analysis		 0.011994
Memory Bandwidth Analysis of Hierarchical Multiprocessors using Model Decomposition and Steady-State Flow Analysis · IEEE Trans. Parallel Distributed Syst. 1994

Methods — techniques the papers use, named apart from their topics

steady-state flow analysis · 0.0model decomposition · 0.0
YearPublicationVenuePosition
1994 Memory Bandwidth Analysis of Hierarchical Multiprocessors using Model Decomposition and Steady-State Flow Analysis
abstract
For memory bandwidth analysis, researchers generally discard requests that are not accepted during a memory cycle. This assumption simplifies the analysis and produces negligible discrepancies with actual results for a system with a non-hierarchical interconnection network. However, the assumption, "the requests that are not occupied during a memory cycle are discarded," cannot be used for a multiprocessor system with a hierarchical interconnection network (HIN), because the error introduced assumption can be several orders of magnitude higher than the actual bandwidth. An improved analytical model to determine the bandwidth of a HIN-based system is presented.>
Syed Masud Mahmud, L. Tissa Samaratunga
 IEEE Trans. Parallel Distributed Syst.2