Demo Data from EDBT 2026 / reviewers in the wild / expert
Ravindra Jejurikar
dblp:74/2496
· DBLP profile ↗
12ranked-venue papers
9as first author
2since 2021 · last 2025
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 7 · 6 first-authorSecurity and privacy · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Cryptographic primitives and cryptanalysis · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Energy-efficient computing · 49% Embedded and real-time systems · 37% Performance modeling and evaluation · 14% |
Topics — the 15 heaviest of 15, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Cryptographic primitives and cryptanalysis
block cipher |
0.9 | 1 | 2025 | Post-quantum Security of Key-Alternating Feistel Ciphers · ASIACRYPT (1) 2025 |
Cryptographic primitives and cryptanalysis › block cipher
feistel network |
0.9 | 1 | 2025 | Post-quantum Security of Key-Alternating Feistel Ciphers · ASIACRYPT (1) 2025 |
Cryptographic primitives and cryptanalysis › block cipher › feistel network
key-alternating feistel |
0.9 | 1 | 2025 | Post-quantum Security of Key-Alternating Feistel Ciphers · ASIACRYPT (1) 2025 |
Cryptographic primitives and cryptanalysis
post-quantum cryptography |
0.9 | 1 | 2025 | Post-quantum Security of Key-Alternating Feistel Ciphers · ASIACRYPT (1) 2025 |
Embedded and real-time systems
real-time scheduling |
0.2 | 4 | 2006 | Energy-aware task scheduling with task synchronization for embedded real-time systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 Optimized Slowdown in Real-Time Task Systems · IEEE Trans. Computers 2006 Dynamic slack reclamation with procrastination scheduling in real-time embedded systems · DAC 2005 |
Energy-efficient computing › voltage scaling
dynamic voltage scaling |
0.2 | 3 | 2006 | Energy-aware task scheduling with task synchronization for embedded real-time systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 Optimized Slowdown in Real-Time Task Systems · IEEE Trans. Computers 2006 Leakage aware dynamic voltage scaling for real-time embedded systems · DAC 2004 |
Energy-efficient computing
power management |
0.2 | 3 | 2006 | Optimized Slowdown in Real-Time Task Systems · IEEE Trans. Computers 2006 Dynamic slack reclamation with procrastination scheduling in real-time embedded systems · DAC 2005 Leakage aware dynamic voltage scaling for real-time embedded systems · DAC 2004 |
Performance modeling and evaluation › performance prediction
slowdown estimation |
0.1 | 2 | 2006 | Energy-aware task scheduling with task synchronization for embedded real-time systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 Optimized Slowdown in Real-Time Task Systems · IEEE Trans. Computers 2006 |
Energy-efficient computing
energy-aware scheduling |
0.1 | 1 | 2006 | Energy-aware task scheduling with task synchronization for embedded real-time systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 |
Energy-efficient computing
leakage power reduction |
0.1 | 1 | 2005 | Dynamic slack reclamation with procrastination scheduling in real-time embedded systems · DAC 2005 |
Embedded and real-time systems › real-time scheduling › resource reclaiming
slack reclaiming |
0.1 | 1 | 2005 | Dynamic slack reclamation with procrastination scheduling in real-time embedded systems · DAC 2005 |
Embedded and real-time systems
real-time embedded systems |
0.0 | 2 | 2005 | Dynamic slack reclamation with procrastination scheduling in real-time embedded systems · DAC 2005 Leakage aware dynamic voltage scaling for real-time embedded systems · DAC 2004 |
Embedded and real-time systems
timing constraints |
0.0 | 2 | 2005 | Dynamic slack reclamation with procrastination scheduling in real-time embedded systems · DAC 2005 Leakage aware dynamic voltage scaling for real-time embedded systems · DAC 2004 |
Mathematical optimization › continuous optimization
convex optimization |
0.0 | 1 | 2006 | Optimized Slowdown in Real-Time Task Systems · IEEE Trans. Computers 2006 |
Mathematical optimization › linear programming
ellipsoid method |
0.0 | 1 | 2006 | Optimized Slowdown in Real-Time Task Systems · IEEE Trans. Computers 2006 |
Methods — techniques the papers use, named apart from their topics
ellipsoid method · 0.1convex optimization · 0.1bisection method · 0.1simulation · 0.1rate monotonic scheduling · 0.1earliest deadline first scheduling · 0.1dynamic voltage scaling · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Post-quantum Security of Key-Alternating Feistel Ciphers
Jyotirmoy Basak, Ritam Bhaumik, Amit Kumar Chauhan, Ravindra Jejurikar, Ashwin Jha 0001, Anandarup Roy 0002, André Schrottenloher, Suprita Talnikar |
ASIACRYPT (1) | 4 |
| 2022 | Farasha: A Provable Permutation-Based Parallelizable PRF
Najwa Aaraj, Emanuele Bellini 0002, Ravindra Jejurikar, Marc Manzano, Raghvendra Rohit 0001, Eugenio Salazar |
SAC | 3 |
| 2006 | Optimized Slowdown in Real-Time Task SystemsabstractSlowdown factors determine the extent of slowdown a computing system can experience based on functional and performance requirements. Dynamic voltage scaling (DVS) of a processor based on slowdown factors can lead to considerable energy savings. We address the problem of computing slowdown factors for dynamically scheduled tasks with specified deadlines. We present an algorithm to compute a near optimal constant slowdown factor based on the bisection method. As a further generalization, for the case of tasks with varying power characteristics, we present the computation of near optimal slowdown factors as a solution to convex optimization problem using the ellipsoid method. The algorithms are practically fast and have the same time complexity as the algorithms to compute the feasibility of a task set. Our simulation results show an average 20 percent energy gain over known slowdown techniques using static slowdown factors and 40 percent gain with dynamic slowdown Ravindra Jejurikar, Rajesh K. Gupta 0001 |
IEEE Trans. Computers | 1 |
| 2006 | Energy-aware task scheduling with task synchronization for embedded real-time systemsabstractSlowdown factors determine the extent of slowdown that a computing system can experience based on functional and performance requirements. Dynamic voltage scaling (DVS) of a processor based on slowdown factors can lead to considerable energy savings. This paper addresses the problem of DVS in the presence of task synchronization. Tasks synchronize to enforce mutually exclusive access to the shared resources and can be blocked by lower priority tasks. Task slowdown factors that guarantee meeting all task deadlines are computed. Both static and dynamic priority scheduling viz. rate monotonic (RM) scheduling and earliest deadline first (EDF) scheduling, respectively, are studied Ravindra Jejurikar, Rajesh K. Gupta 0001 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2005 | Dynamic slack reclamation with procrastination scheduling in real-time embedded systemsabstractLeakage energy consumption is an increasing concern in current and future CMOS technology generations. Procrastination scheduling, where task execution can be delayed to maximize the duration of idle intervals, has been proposed to minimize leakage energy drain. The authors addressed dynamic slack reclamation techniques under procrastination scheduling to minimize the static and dynamic energy consumption. In addition to dynamic task slowdown, a dynamic procrastination was proposed, which seeks to extend idle intervals through slack reclamation. While using the entire slack for either slowdown or procrastination need not be the most energy efficient approach, the slack was distributed between slowdown and procrastination to exploit maximum energy savings. The simulation experiments showed that dynamic slowdown result on an average 10% energy gains over static slowdown. Dynamic procrastination extends the average sleep interval by 25%, which reduces the idle energy consumption by 15%, while meeting all timing requirements. Ravindra Jejurikar, Rajesh K. Gupta 0001 |
DAC | 1 |
| 2005 | Energy Aware Non-Preemptive Scheduling for Hard Real-Time SystemsabstractSlowdown based on dynamic voltage scaling (DVS) provides the ability to perform an energy-delay tradeoff in the system. Nonpreemptive scheduling becomes an integral part of systems where resource characteristics makes preemption undesirable or impossible. We address the problem of energy efficient scheduling of nonpreemptive tasks based on the earliest deadline first (EDF) scheduling policy. We present the stack based slowdown algorithm that builds upon the optimal feasibility test for nonpreemptive systems. We also propose a dynamic stack reclamation policy to further enhance energy savings. Simulation results show on an average 15% energy savings using static slowdown factors and 20% savings with dynamic slowdown, over known slowdown techniques. Ravindra Jejurikar, Rajesh K. Gupta 0001 |
ECRTS | 1 |
| 2004 | Leakage aware dynamic voltage scaling for real-time embedded systemsabstractA five-fold increase in leakage current is predicted with each technology generation. While Dynamic Voltage Scaling (DVS) is known to reduce dynamic power consumption, it also causes increased leakage energy drain by lengthening the interval over which a computation is carried out. Therefore, for minimization of the total energy, one needs to determine an operating point, called the critical speed. We compute processor slowdown factors based on the critical speed for energy minimization. Procrastination scheduling attempts to maximize the duration of idle intervals by keeping the processor in a sleep/shutdown state even if there are pending tasks, within the constraints imposed by performance requirements. Our simulation experiments show that the critical speed slowdown results in up to 5% energy gains over a leakage oblivious dynamic voltage scaling. Procrastination scheduling scheme extends the sleep intervals to up to 5 times, resulting in up to an additional 18% energy gains, while meeting all timing requirements. Ravindra Jejurikar, Cristiano Pereira, Rajesh K. Gupta 0001 |
DAC | 1 |
| 2004 | Optimized Slowdown in Real-Time Task Systems
Ravindra Jejurikar, Rajesh K. Gupta 0001 |
ECRTS | 1 |
| 2004 | Dynamic voltage scaling for systemwide energy minimization in real-time embedded systemsabstractTraditionally, dynamic voltage scaling (DVS) techniques have focused on minimizing the processor energy consumption as opposed to the entire system energy consumption. The slowdown resulting from DVS can increase the energy consumption of components like memory and network interfaces. Furthermore, the leakage power consumption is increasing with the scaling device technology and must also be taken into account. In this work, we consider energy efficient slowdown in a real-time task system. We present an algorithm to compute task slowdown factors based on the contribution of the processor leakage and standby energy consumption of the resources in the system. Our simulation experiments using randomly generated task sets show on an average 10% energy gains over traditional dynamic voltage scaling. We further combine slowdown with procrastination scheduling which increases the average energy savings to 15%. We show that our scheduling approach minimizes the total static and dynamic energy consumption of the systemwide resources. Ravindra Jejurikar, Rajesh K. Gupta 0001 |
ISLPED | 1 |
| 2004 | Procrastination scheduling in fixed priority real-time systemsabstractProcrastination scheduling has gained importance for energy efficiency due to the rapid increase in the leakage power consumption. Under procrastination scheduling, task executions are delayed to extend processor shutdown intervals, thereby reducing the idle energy consumption. We propose algorithms to compute the maximum procrastination intervals for tasks scheduled by either the fixed priority or the dual priority scheduling policy. We show that dual priority scheduling always guarantees longer shutdown intervals than fixed priority scheduling. We further combine procrastination scheduling with dynamic voltage scaling to minimize the total static and dynamic energy consumption of the system. Our simulation experiments show that the proposed algorithms can extend the sleep intervals up to 5 times while meeting the timing requirements. The results show up to 18% energy gains over dynamic voltage scaling. Ravindra Jejurikar, Rajesh K. Gupta 0001 |
LCTES | 1 |
| 2002 | Energy aware task scheduling with task synchronization for embedded real time systemsabstractSlowdown factors determine the extent of slowdown a computing system can experience based on functional and performance requirements. Dynamic Voltage Scaling (DVS) of a processor based on slowdown factors can lead to considerable energy savings. The problem of DVS in the presence of task synchronization has not yet been addressed. We compute slowdown factors for tasks which synchronize for access to shared resources. Tasks synchronize to enforce mutually exclusive access to these resources and can be blocked by lower priority tasks. We compute static slowdown factors for the tasks which guarantee meeting all the task deadlines. Our simulation experiments show on an average 25% energy gains over the known slowdown techniques. Ravindra Jejurikar, Rajesh K. Gupta 0001 |
CASES | 1 |
| 2000 | Timing driven co-design of networked embedded systemsabstractAdvances in microelectronics integration have led to emergence of tightly integrated systems with high performance network interfaces. Design of such systems especially for single chip implementation is a delicate balance of functionality and available time budget to perform the tasks. Computer-aided design tools and methodologies are needed to ensure the correctness of the design and eciency of the design process, especially for networked systems that have strict timing requirements both due to technology as well as networking needs. We present an overview of a timing-driven design methodology for networked systems, developed at the University of California, Irvine. I. Introduction Networked embedded systems (NES) are distributed embedded systems connected together using network interfaces and standardized protocols. The protocols are often implemented partly in hardware and partly in software. NES are usually designed at the highest level of abstraction as a collection of basic net... Dinesh Ramanathan, Ravindra Jejurikar, Rajesh K. Gupta 0001 |
ASP-DAC | 2 |