To effectively transmit data to and from satellites requires a complex and robust RF communication system. Using adaptive link techniques, several different types of signal modulations may be used to maximize satellite efficiency depending on a variety of unexpected channel impairments. We propose an FPGA based neural network system capable of learning these RF signal modulations using a supervised learning technique designed for low power, high-efficiency in-orbit deployment. Thus, as signal modulation changes, a receiving satellite would be able to recognize this modulation update without adjustment from an operator, or any delay due to control signal transmission.Due to the limited resources of FPGAs, we implement CNN transfer learning on the FPGA instead of full CNN training. The work presented demonstrates a convolutional neural network (CNN) capable of learning and recognizing a set of modulation schemes commonly used to transmit RF information. We are capable of recognizing the modulation scheme from the I and Q data channels directly, with no preprocessing or data conversion required other than segmenting the incoming signal into a set of uniform normalized samples. We perform a network design and size analysis, showing that we can obtain reasonably high accuracy using networks with a relatively low number of trainable parameters. Thus, modulation recognition can be performed through rapid feedforward computation. Given that a user of this system may wish to receive a signal using a modulation scheme that the network has not previously learned, we demonstrate that transfer learning can learn new modulation schemes by retraining only the fully connected layers in the CNN. Thus, this type of network would excel in outer space deployment using high-efficiency transfer learning hardware. Our FPGA system utilized 2.1W power and processed 219 data samples per second for training. This made it about 59x more energy efficient than a desktop GPU for the same task.

Detecting anomalies and faults swiftly and accurately is essential in many applications, such as healthcare, infrastructure, industry, and security. In most of these applications, the available power for running an anomaly detection system is very limited. This is especially the case for modern smart and electric vehicles, which have an increasing amount of electronics. These vehicles have Electronic Control Units (ECUs) that communicate with each other through the Controller Area Network (CAN) bus. The Controller Area Network, however, is not very secure, so bad actors can do severe damage, putting the lives of drivers and passengers at risk. Thus, low-power anomaly detection is essential for both security and reliability. Deep learning networks have demonstrated proficiency in anomaly identification. However, their implementation on conventional Central Processing Units (CPUs) and Graphics Processing Units (GPUs) incurs significant energy consumption. To overcome this limitation, we propose a low-power approach for placing security directly in the network hardware. An autoencoder-based real-time anomaly detector trained through unsupervised learning is seamlessly mapped onto the Intel Loihi spiking neuromorphic processor. Our proposed anomaly detector used significantly less power than a CPU or GPU and showed the best accuracy and F-1 score to detect anomalies compared to the alternative spiking approaches. The proposed anomaly detection system consumed about 20,000 and 700 times less energy than a CPU and GPU respectively. To the best of our knowledge, this is the first low-power, unsupervised anomaly detection system using the Loihi or any other neuromorphic processor. The results of this work will apply to other anomaly detection applications, as well as other spiking neuromorphic processors, resulting in a universally applicable extreme low-power anomaly detection platform.

There is increasing demand for specialized hardware for training deep neural networks (DNNs), both in edge/IoT environments and in high-performance computing systems. The design space of such hardware is very large due to the wide range of processing architectures, DNN configurations, and dataflow options. This makes developing DNN processors quite complex, especially for training. We present TRIM, an infrastructure to help hardware architects explore the design space of DNN accelerators for both inference and training in the early design stages. The model evaluates at the whole network level, considering both interlayer and intralayer activities. Given applications, essential hardware specifications, and a design goal, TRIM can quickly explore different hardware design options, select the optimal dataflow and guide new hardware architecture design. We validated TRIM with FPGA-based implementation of DNN accelerators and ASIC-based architectures. We also show how to use TRIM to explore the design space through several case studies. TRIM is a powerful tool to help architects evaluate different hardware choices to develop efficient inference and training architecture design. Experimental results show that TRIM is a powerful tool for rapidly exploring the design space of DNN architectures for training and inference.

Artificial Intelligence (AI) is moving towards the edge. Training an AI model for edge computing on a centralized server increases latency, and the privacy of edge users is jeopardized due to private data transfer through a less secure communication channels. Additionally, existing high-power computing systems are battling with memory and data transfer bottlenecks between the processor and memory. Federated Learning (FL) is a collaborative AI learning paradigm for distributed local devices that operates without transferring local data. Local participant devices share the updated network parameters with the central server instead of sending the original data. The central server updates the global AI model and deploys the model to the local clients. As the local data resides only on the edge, these devices need to be protected from cyberattacks. The Federated Intrusion Detection System (FIDS) could be a viable system to protect edge devices as opposed to a centralized protection system. However, on-device training of the model in resource constrained devices may suffer from excessive power drain, in addition to memory and area overhead. In this work we present a memristor based system for AI training on edge devices. Memristor devices are ideal candidates for processing in memory, as their dynamic resistance properties allow them to perform multiply-add operations in parallel in the analog domain with extreme efficiency. Alternatively, existing CMOS-based PIM systems are typically developed for edge inference based on pretrained weights, and are not equipped for on-chip training. We show the effectiveness of the system, where successful learning and recognition is achieved completely within edge devices. The classification accuracy of the memristor system shows negligible loss when compared a software implementation. To the best of our knowledge, this first demonstration of a memristor based federated learning system. We demonstrate the effectiveness of this system as an intrusion detection platform for edge devices, although given the flexibility of the learning algorithm, it could be used to enhance many types of on board leaning and classification applications.

Spiking neural networks represent a transition from deep networks and tensor engines to more dynamic systems better suited for carrying out decisions based on temporal patterns within data. Furthermore, memristor based hardware for synaptic computation provides the potential for dramatic gains in terms of portability, power reduction, and throughput efficiency. In this paper we combine these ideas and present a memristor crossbar based implementation of a liquid state machine based on spiking neurons. The design is verified by demonstrating successful classification of MIDI (Musical Instrument Digital Interface) signals. Given the temporal nature of musical works, this dataset is well suited to show the effectiveness of the proposed hardware. The proposed circuit implementing this LSM is designed using SPICE to ensure accuracy at the device level, which aids in detailed analysis and circuit optimizations. Liquid layer activity is converted to state vectors using custom hardware that does not bottleneck throughput. Along with the proposed architecture, a neuron modeling procedure is described to match the software and hardware spiking neuron outputs, proving the feasibility of a full-scale implementation of the LSM system. Furthermore, various non-idealities are analyzed in the network, including misfiring neurons and noise associated with updating memristor conductance. We find that the proposed architecture is resilient to noise and fault-tolerant. In simulation, the performance of the memristor-based LSM is demonstrated on a musical genre classification experiment, where a recognition accuracy of 90% is achieved, compared to 91% accuracy in software. To the best of our knowledge this work represents the first end to end circuit implementation of an analog spiking neural network based reservoir computing system where memristors are responsible for all computation, with custom CMOS hardware for sampling the liquid layer. Finally, we tie the work together with an energy and timing analysis of the proposed system.

In many cases, low power autonomous systems need to make decisions extremely efficiently. However, as a potential solution space becomes more complex, finding a solution quickly becomes nearly impossible using traditional computing methods. Thus, in this work we present a constraint satisfaction algorithm based on the principles of spiking neural networks. To demonstrate the validity of this algorithm, we have shown successful execution of the Boolean satisfiability problem (SAT) on the Intel Loihi spiking neuromorphic research processor. Power consumption in this spiking processor is due primarily to the propagation of spikes, which are the key drivers of data movement and processing. Thus, this system is inherently efficient for many types of problems. However, algorithms must be redesigned in a spiking neural network format to achieve the greatest efficiency gains. To the best of our knowledge, the work in this paper exhibits the first implementation of constraint satisfaction on a low power embedded neuromorphic processor. With this result, we aim to show that embedded spiking neuromorphic hardware is capable of executing general problem solving algorithms with great areal and computational efficiency.

Compact online learning architectures can be used to enhance internet of things devices, allowing them to learn directly on received data instead of sending data to a remote server for learning. This saves communication energy and enhances privacy and security, as the data is not shared. This paper presents a 3D memristor based multicore architecture capable of on-line learning, where a mixed signal design utilizes memristor crossbars to both store synaptic weights and to carry out analog dot product computations. A 3D memristor architecture is one where several memristor crossbars are stacked vertically on top of each other to reduce the area footprint of a chip. A variety of deep learning applications can be processed using the proposed architecture, and we show how the simulated architecture is able to learn and classify several datasets. In this work we also examine how changing the number of vertically stacked crossbars within a neural core impacts energy, time, and area requirements of the architecture.

In many cases, low power autonomous systems need to make decisions extremely efficiently. However, as a problem space becomes more complex, finding a solution quickly becomes nearly impossible using traditional computing methods. Thus, in this work we show that constraint satisfaction problems (CSPs) can be solved quickly and efficiently using spiking neural networks. Constraint satisfaction is a general problem solving technique that can be applied to a large number of different applications. To demonstrate the validity of this algorithm, we show successful execution of the Boolean satisfiability problem (SAT) on the Intel Loihi spiking neuromorphic research processor. In many cases, constraint satisfaction problems have solution sets as opposed to single solutions. Therefore, the manycore architecture of the Loihi chip is used to parallelize the solution finding process, leading to a quasi-complete solution set generated at extreme efficiency (dynamic energy as low as 8 micro joules per solution). Power consumption in this spiking processor is due primarily to the propagation of spikes, which are the key drivers of data movement and processing. Thus, the proposed SAT algorithm was customized for spiking neural networks to achieve the greatest efficiency gains. To the best of our knowledge, the work in this paper exhibits the first implementation of constraint satisfaction on a low power embedded neuromorphic processor capable of generating a solution set. In general, we show that embedded spiking neuromorphic hardware is capable parallelizing the constraint satisfaction problem solving process to yield extreme gains in terms of time, power, and energy.

This paper presents a memristive device model capable of accurately matching a wide range of characterization data collected from a tantalum oxide memristor. Memristor models commonly use a set of equations and fitting parameters to match the complex dynamic conductivity pattern observed in these devices. Along with the proposed model, a procedure is also described that can be used to optimize each fitting parameter in the model relative to an I-V curve. Therefore, model parameters are self-updated based on this procedure when a new cyclic I-V sweep is provided for model optimization. This model will automatically provide the best possible match to the characterization data without any additional optimization from the user. In this paper, multiple cyclic I-V characterizations are modeled from ten different tantalum oxide devices (on the same wafer). Additionally, studies were completed to demonstrate the amount of variation present between devices on a wafer, as well as the amount of variation present within a single device. Methods for modeling this variation are then proposed, resulting in an accurate and complete, automated, memristor modeling approach.

This paper describes a simulated memristor-based neuromorphic system that can be used for ex-situ training of a multi-layer perceptron algorithm. The presented programming technique can be used to map the weights required of a neural algorithm directly onto the grid of resistances in a memristor crossbar. Using this weight-to-crossbar mapping approach along with the dot product calculation circuit, neural algorithms can be easily implemented using this system. To show the effectiveness of this circuit, a Multilayer Perceptron is trained to perform Sobel edge detection. Following these simulations, an analysis was presented that shows how memristor programming accuracy and network size are related to output error; the results show that network size can be increased to reduce testing error. In some cases, the memristors in the circuit may be capable of operating with at lower precision if the network size is increased. This means that less precise (or lower resolution) memristor devices may be used to implement the proposed system. Furthermore, a power, timing, and energy analysis shows that this circuit has a computation throughput that allows it to process 4K UHD video in real time at approximately 337mW.

Cognitive agents are typically utilized in autonomous systems for automated decision making. These systems interact at real time with their environment and are generally heavily power constrained. Thus, there is a strong need for a real time agent running on a low power platform. The agent examined is the Cognitively Enhanced Complex Event Processing (CECEP) architecture. This is an autonomous decision support tool that reasons like humans and enables enhanced agent-based decision-making. It has applications in a large variety of domains including autonomous systems, operations research, intelligence analysis, and data mining. One of the key components of CECEP is the mining of knowledge from a repository described as a Cognitive Domain Ontology (CDO). One problem that is often tasked to CDOs is asset allocation. Given the number of possible solutions in this allocation problem, determining the optimal solution via CDO can be very time consuming. In this work we show that a grid of isolated spiking neurons is capable of generating solutions to this problem very quickly, although some degree of approximation is required to achieve the speedup. However, the approximate spiking approach presented in this work was able to complete all allocation simulations with greater than 99.9% accuracy. To show the feasibility of low power implementation, this algorithm was executed using the Intel Loihi manycore neuromorphic processor. Given the vast increase in speed (greater than 1000 times in larger allocation problems), as well as the reduction in computational requirements, the presented algorithm is ideal for moving asset allocation to low power, portable, embedded hardware.

Declarative memory enables cognitive agents to effectively store and retrieve factual memory in real-time. Increasing the capacity of a real-time agent's declarative memory increases an agent's ability to interact intelligently with its environment but requires a scalable retrieval system. This work represents an extension of the Accelerated Declarative Memory (ADM) system, referred to as Hardware Accelerated Declarative Memory (HADM), to execute retrievals on a GPU. HADM also presents improvements over ADM's CPU execution and considers critical behavior for indefinitely running declarative memories. The negative effects of a constant maximum associative strength are considered, and mitigating solutions are proposed. HADM utilizes a GPU to process the entire semantic network in parallel during retrievals, yielding significantly faster declarative retrievals. The resulting GPU-accelerated retrievals show an average speedup of approximately 70 times over the previous Service Oriented Architecture Declarative Memory (soaDM) implementation and an average speedup of approximately 5 times over ADM. HADM is the first GPU-accelerated declarative memory system in existence.

In the last decade, special purpose computing systems, such as Neuromorphic computing, have become very popular in the field ofcomputer vision and machine learning for classification tasks. In 2015, IBM's released the TrueNorth Neuromorphic system, kick-starting a new era of Neuromorphic computing. Alternatively, Deep Learning approaches such as Deep Convolutional Neural Networks (DCNN) show almost human-Ievel accuracies for detection and classification tasks. IBM's 2016 release of a deep learning framework for DCNNs, called Energy Efficient Deep Neuromorphic Networks (Eedn). Eedn shows promise for delivering high accuracies across a number of different benchmarks, while consuming very low power, using IBM's TrueNorth chip. However, there are many things that remained undiscovered using the Eedn framework for classification tasks on a Neuromorphic system. In this paper, we have empirically evaluated the performance of different DCNN architectures implemented within the Eedn framework. The goal of this work was discover the most efficient way to implement DCNN models for object classification tasks using the TrueNorth system. We performed our experiments using benchmark data sets such as MNIST, COIL-20, and COIL-100. The experimental results show very promising classification accuracies with very low power consumption on IBM's NSle Neurosynaptic system. The results show that for datasets with large numbers of classes, wider networks perform better when compared to deep networks comprised of nearly the same core complexity on IBM's TrueNorth system.

Deep learning, Recurrent Neural Networks (RNN) in particular have shown superior accuracy in a large variety of tasks including machine translation, language understanding, and movie frames generation. However, these deep learning approaches are very expensive in terms of computation. In most cases, Graphic Processing Units (GPUs) are in used for large scale implementations. Meanwhile, energy efficient RNN approaches are proposed for deploying solutions on special purpose hardware including Field Programming Gate Arrays (FPGAs) and mobile platforms. In this paper, we propose an effective quantization approach for Recurrent Neural Networks (RNN) techniques including Long Short-Term Memory (LSTM), Gated Recurrent Units (GRU), and Convolutional Long Short Term Memory (ConvLSTM). We have implemented different quantization methods including Binary Connect {-1, 1}, Ternary Connect {-1, 0, 1}, and Quaternary Connect {-1, -0.5, 0.5, 1}. These proposed approaches are evaluated on different datasets for sentiment analysis on IMDB and video frame predictions on the moving MNIST dataset. The experimental results are compared against the full precision versions of the LSTM, GRU, and ConvLSTM. They show promising results for both sentiment analysis and video frame prediction.

Edge devices often have to processdata at low power and would benefit from being adaptable. Given that the data coming into these devices is generally unlabeled, unsupervised training on these devices is beneficial. This paper examines a low power approach to implement the winner takes all algorithm, for self-organizing maps through a memristor crossbar based circuit. A novel neuron circuit is designed for the winning neuron detection and lateral inhibition operations. Our experimental results show that the proposed system can self-organize based on unlabeled training data. The proposed design was around 0.002mm$^{\mathbf{2\, $textbf{{in area and consumed about 0.2mW of power. When compared to a CPU, the design had a higher error rate, but was 100 times faster and consumed much lower area and power. Thus when area or power reduction are crucially important, this approach is quite viable.

Specialized ultra-low power deep learning architectures with on-chip training capability can be useful in variety of applications that require adaptability. This paper presents such a processor design, Socrates-D 2.0, a multicore architecture for deep neural network based training and inference. The architecture consists of a set of processing cores, each with internal memories to store synaptic weights. Additionally, we present a method to map traditional deep learning networks to our multicore architecture and show that there is minimal impact in training accuracy. The system level area and power benefits of the specialized architecture are compared with the earlier generation of Socrates-D. Our experimental evaluations show that the proposed architecture can provide 1.25× area and 1.19× energy efficiency than the previous version of Socrates-D.

Custom low power hardware for network intrusion detection is in great demand, as this would allow for efficient security in battery-powered network devices. This paper presents a memristor crossbar based Multilayer Perceptron (MLP) capable of performing network intrusion detection. The MLP is trained based on the Knowledge Discovery and Datamining (KDD) dataset. Once the network is trained, the weight values are programmed into a simulated memristor crossbar hardware system to show that custom circuitry can be designed to perform on-chip intrusion detection. We show the proposed memristor system is capable of achieving greater than 99% intrusion detection accuracy if the memristors utilized are able to store at least 4 unique values (essentially acting as 2-bit devices). Furthermore, we present a number of studies that quantify the amount of classification accuracy lost due to analog processing and amplification in the signal path. This circuit is capable of tolerating significant amplifier gain error (up to 30%) before classification accuracy drops below 99%.

Deep packet inspection (DPI) is a critical component to prevent intrusion detection. This requires a detailed analysis of each network packet header and body. Although this is often done on dedicated high-power servers in most networked systems, mobile systems could potentially be vulnerable to attack if utilized on an unprotected network. In this case, having DPI hardware on the mobile system would be highly beneficial. Unfortunately, DPI hardware is generally area and power consuming, making its implementation difficult in mobile systems. We developed a memristor crossbar-based approach, inspired by memristor crossbar neuromorphic circuits, for a low-power, low-area, and high-throughput DPI system that examines both the header and body of a packet. Two key types of circuits are presented: static pattern matching and regular expression circuits. This system is able to reduce execution time and power consumption due to its high-density grid and massive parallelism. Independent searches are performed using low-power memristor crossbar arrays giving rise to a throughput of 160Gbps with no loss in the classification accuracy.

In recent years, Convolutional Neural Networks (CNNs) have become very popular and have achieved great success in many computer vision tasks - particularly in object recognition. Partially inspired by neuroscience, CNNs share many properties with the visual system of the brain. However, the filters of convolutional layers play a vital role on overall accuracy of CNNs. In this paper, the Cellular Simultaneous Recurrent Networks (CSRNs) are applied to generate initial filters of Convolutional Networks (CNs) for features extraction and Regularized Extreme Learning Machines (RELM) are used for classification. Furthermore, Deep Belief Networks (DBN), CNNs with random and Gabor filters are implemented to evaluate the overall performance against the proposed CSRN's filters based CNs with RELM. Experiments were conducted on three popular datasets for object recognition (such as face, pedestrian, and car) to evaluate the performance of the proposed system. The experimental results show that in most of the cases, the proposed approach provides better performance on the extracted features using CSRN's filters with CNs compare to initialize with Gaussian random and DBN for object recognition.

Image features can be learned and subsequently used for reconstruction and classification tasks in the fields of machine learning and computer vision. In this work, we propose image reconstruction using Convolutional Sparse Coding (CSC) on IBM's TrueNorth Neuromorphic computing system. CSC explicitly models local interactions through the convolution operations. Convolutional kernels define a dictionary and Sparse Feature Maps (SFMs) that are generated through a training process. The images are reconstructed with convolutional operations on SFMs and respective kernels. In this paper, we report on experimental results demonstrating promising sparse reconstructions on the IBM Neuromorphic TrueNorth hardware for two different benchmarks: MNIST and CIFAR-10. It is noted that this is the first ever important step towards convolutional sparse coding on neuromorphic hardware.

The problems of Artificial intelligence (AI) naturally maps to NP-hard optimization problems. This trend has significance to achieve human-level computation capability from machines. This computational ability can be achieved by developing evolutionary algorithms or mapping those evolutionary algorithms onto new generation computing systems: Quantum or Neuromorphic hardware. In this paper, we implemented the NP-hard optimization problem called Quadratic Unconstrained Binary Optimization (QUBO) problem for the solution of graph problems on the IBM's Neurosynaptic TrueNorth System. We have experimented on different types of graph problems with different levels of complexities and achieved encouraging results on IBM's Neuromorphic TrueNorth chip. Moreover, there are a set of potential applications have been discussed based on this proposed QUBO solution. Along with the QUBO on quantum annealing, it is the important first step towards the solutions of QUBO on Neuromorphic computing systems.

In the paper, we demonstrate a neuromorphic cognitive computing approach for Network Intrusion Detection System (IDS) for cyber security using Deep Learning (DL). The algorithmic power of DL has been merged with fast and extremely power efficient neuromorphic processors for cyber security. In this implementation, the data has been numerical encoded to train with un-supervised deep learning techniques called Auto Encoder (AE) in the training phase. The generated weights of AE are used as initial weights for the supervised training phase using neural networks. The final weights are converted to discrete values using Discrete Vector Factorization (DVF) for generating crossbar weight, synaptic weights, and thresholds for neurons. Finally, the generated crossbar weights, synaptic weights, threshold, and leak values are mapped to crossbars and neurons. In the testing phase, the encoded test samples are converted to spiking form by using hybrid encoding technique. The model has been deployed and tested on the IBM Neurosynaptic Core Simulator (NSCS) and on actual IBM TrueNorth neurosynaptic chip. The experimental results show around 90.12% accuracy for network intrusion detection for cyber security on the physical neuromorphic chip. Furthermore, we have investigated the proposed system not only for detection of malicious packets but also for classifying specific types of attacks and achieved 81.31% recognition accuracy. The neuromorphic implementation provides incredible detection and classification accuracy for network intrusion detection with extremely low power.

This paper presents on-chip training circuits for memristor based deep neural networks utilizing unsupervised and supervised learning methods. Memristor crossbar circuits allow neural algorithms to be implemented very efficiently, but could be prone to device variations and faults. On chip training circuits would allow the training algorithm to account for device variability and faults in these circuits. We have utilized autoencoders for layer-wise pre-training of the deep networks and utilized the back-propagation algorithm for supervised fine tuning. Our design utilizes two memristors per synapse for higher precision of weights. We have demonstrated successful training of memristor based deep networks for the MNIST digit classification and the KDD intrusion detection datasets.

Cognitive agents are typically utilized in autonomous systems for automated decision making. These systems interact at real time with their environment and are generally heavily power constrained. Thus there is a strong need for a real time agent running on a low power computing platform. This paper examines how some of the components of a cognitive agent can be mapped onto the IBM TrueNorth neurosynaptic system to achieve real time performance at low power. The agent examined is the Cognitively Enhanced Complex Event Processing (CECEP) architecture. This is an autonomous decision support tool that reasons like humans and enables enhanced agent-based decision-making. It has applications in a large variety of domains including autonomous systems, operations research, intelligence analysis, and data mining. One of the most time consuming and key components of CECEP is the mining of knowledge from a repository described as a Cognitive Domain Ontology (CDO). This paper looks at how CDOs can be mapped into neural form for realtime applications, and then examines their implementation on the IBM TrueNorth processor. The results show that the TrueNorth implementation generated correct answers for all the CDOs examined.

This paper presents a simulated memristor crossbar based Convolutional Neural Network (CNN). Deep networks implemented on GPU clusters have become the state of the art in providing excellent classification ability, at the cost of a more complex data manipulation process. In this work we show that once deep networks are trained, the analog crossbar circuits in this paper can parallelize the recognition phase of a CNN algorithm. With the massively parallel structure proposed in this work, we are able to generate multiple output feature maps in a single processing cycle. We show the proposed system is capable of operating with a negligible loss in classification accuracy if the memristors utilized are able to store at least 16 unique values (essentially acting as 4-bit devices). Furthermore, we quantify the amount of classification accuracy lost due to analog amplification in the signal path. To the best of our knowledge, this is the first paper that presents a memristor based circuit that is able to completely parallelize the CNN recognition process.

Memristor crossbars are capable of implementing learning algorithms in a much more energy and area efficient manner compared to traditional systems. However, the programmable nature of memristor crossbars must first be explored on a smaller scale to see which memristor device structures are most suitable for applications in reconfigurable computing. In this paper, we demonstrate the programmability of memristor devices with filamentary switching based on LiNbOx, a new resistive switching oxide. We have performed several characterization experiments that demonstrate the high resolution programmability of these devices. Once the optimal programming voltages and conductivity ranges for these memristor devices are determined, a method is presented to determine how many unique states can be achieved in these devices. Parameters obtained from this analysis can greatly strengthen memristor device models that implement realistic stochastic switching behavior. We show that 11 unique states can be stored in this device with 95% confidence, but many more states are achievable using feedback write techniques or in-situ learning. Therefore, we have determined that Lithium Niobate memristors are strong candidates for use in neuromorphic computing.

This paper presents a simulated memristor crossbar implementation of a deep Convolutional Neural Network (CNN). In the past few years deep neural networks implemented on GPU clusters have become the state of the art in image classification. They provide excellent classification ability at the cost of a more complex data manipulation process. However once these systems are trained, we show that the analog crossbar circuits in this paper can highly parallelize the recognition phase of a CNN algorithm. One of the drawbacks of using memristors to carry out computations is that the data stored will likely have less precision when compared to typical 32-bit floating point memory. However, we show the proposed system is capable of operating with zero loss in classification accuracy if the memristors utilized are able to store at least 16 unique values (essentially acting as 4-bit devices). To the best of our knowledge, this is the first paper that presents a memristor based circuit for implementing CNN recognition. This is also the first paper that provides a circuit for precise memristor based analog convolution.

Extreme Learning Machine (ELM) has been introduced as a new algorithm for training single hidden layer feed-forward neural networks (SLFNs) instead of the classical gradient-based algorithms. Based on the consistency property of data, which enforce similar samples to share similar properties, ELM is a biologically inspired learning algorithm with SLFNs that learns much faster with good generalization and performs well in classification applications. However, the random generation of the weight matrix in current ELM based techniques leads to the possibility of unstable outputs in the learning and testing phases. Therefore, we present a novel approach for computing the weight matrix in ELM which forms a State Preserving Extreme Leaning Machine (SPELM). The SPELM stabilizes ELM training and testing outputs while monotonically increases its accuracy by preserving state variables. Furthermore, three popular feature extraction techniques, namely Gabor, Pyramid Histogram of Oriented Gradients (PHOG) and Local Binary Pattern (LBP) are incorporated with the SPELM for performance evaluation. Experimental results show that our proposed algorithm yields the best performance on the widely used face datasets such as Yale, CMU and ORL compared to state-of-the-art ELM based classifiers.

This paper describes a novel memristor-based neuromorphic circuit that can be used for ex-situ training of multi-layer neural network algorithms. The presented ex-situ programming technique can be used to map many key neural algorithms directly onto the grid of resistances in a memristor crossbar. This is possible because the proposed circuit is capable of calculating a true dot product. Existing circuits provide an approximated dot product based on a summation of conductance values, which is inaccurate due to the parallel structure of the crossbar. To show the effectiveness and versatility of this circuit, three different powerful neural networks were simulated. These include a Restricted Boltzmann Machine (RBM) for character recognition, a Convolutional Neural Network (CNN) also for character recognition, and a Multilayer Perceptron (MLP) trained to perform Sobel edge detection. Finally, an architecture analysis was performed showing that neuromorphic processors based on these memristor crossbar circuits can be up to 5 orders of magnitude more power efficient than a RISC processor.

The Cognitively Enhanced Complex Event Processing (CECEP) architecture is an autonomous decision support tool that reasons and learns like humans and enables enhanced agent-based decision making. This architecture has applications in both military and civilian domains, including operations research and data mining. One of the most computationally challenging aspects of CECEP is mining domain knowledge captured in cognitive domain ontologies (CDOs). This requires massively linked knowledge databases to be searched based on a large set of constraints to generate intelligent decisions. The solution search for CDOs is a kind of Constraint Satisfaction Problem (CSP). Due to the unique nature of the CDO-to-CSP mapping, generic constraint solvers are inefficient. We introduce a novel high performance path based forward checking CSP algorithm to solve CDOs and compare it to a commonly utilized CSP solving application. Additionally our approach enables a very compact and efficient representation of the entire solution space to allow fast processing and give agents key ideas on how to further reduce the solution space. The proposed algorithm provided a speedup of about 10-25 times for generating the first solution and about half a million times for all the solutions over a Choco based conventional CSP approach.

This paper describes the acceleration of the declarative knowledge retrieval system of a cognitive architecture, namely ACT-R. The core of ACT-R's retrieval mechanism, activation calculation, is accelerated through leveraging the speed of C++ and the MapReduce program model. Work described in this paper represents an extension of previous Erlang-based concurrent activation. ACT-R's retrieval process is re-examined and optimized in this solution. Concurrency available in the execution platform is exploited to maximize the acceleration of declarative retrieval. The resulting implementation, referred to as Accelerated Declarative Memory (ADM), presents a high-performance activation calculation that enables practical use of more massive declarative memories. ADM presents new mechanisms to access and traverse declarative memory to reduce the overhead of executing retrievals. This solution offers retrieval latencies 20 times faster than the previous Erlang solution.

Recent studies have shown that memristor crossbar based neuromorphic hardware enables high performance implementations of neural networks at low power and in low chip area. This paper presents circuits to train a cascaded set of memristor crossbars representing a multi-layered neural network. The circuits presented implement back-propagation training and would enable on-chip training of memristor crossbars. On-chip training of memristor crossbars can be necessary to overcome the effect of device variability and alternate current paths within crossbars being used as neural networks. We model the memristor crossbars in SPICE in order capture alternate current paths and the impact of wire resistance. Our design can be scaled to multiple neural layers and multiple output neurons. We demonstrate the training of up to three layered neural networks evaluating non-linearly separable functions through detailed SPICE simulations. This is the first study in the literature we have seen that examines the implementation of back-propagation based training of memristor crossbar circuits. The impact of this work would be to enable the design of highly energy efficient and compact neuromorphic processing systems that can be trained to implement large deep networks (such as deep belief networks).

This paper describes memristor-based neuromorphic circuits for non-linear separable pattern recognition. We initially describe a memristor based neuron circuit and then show how multilayer neural networks can be constructed using this neuron circuit. These neuromorphic circuits are capable of learning both linearly and non-linearly separable logic functions. This paper presents the first study of applying neural network learning algorithms to these circuits in SPICE. Our simulations capture alternate current paths within the memristor crossbars and wire resistances that are essential to properly model in crossbar circuits. Our results show that neural network learning algorithms are able to train around these alternate current paths. Further, it was shown that neural networks can properly train the passive memristor-based crossbars without having to use virtual ground mode operational amplifiers as suggested in previous work. Our circuit requires in-situ training, but reduces the number of transistors required by the circuit by about 3 times and reduced the circuit power consumption almost 2 orders of magnitude compared to a virtual ground approach. The key impact of this study is the demonstration through low level circuit simulations that dense memristor crossbars can be effectively utilized to build neuromorphic processors.

Specialized multi-core architectures can provide significant speedups for neural network applications. In this study, we examined the on-chip routing network bandwidth requirements for such architectures processing large multi-layered feed forward neural networks in a pipelined manner. Two on-chip routing network topologies were examined: mesh networks and hybrid bus-mesh networks. Two routing bandwidth models were developed for each network topology: one examined sending neuron outputs from one layer to the next, while the other examined the streaming of synaptic weights from off-chip memory. The model was validated through several simulations studies. For both mesh and bus-mesh interconnection area and power of the on-chip routing network was estimated using the Orion on-chip network tool. Our results show that in multi-core neuromorphic architectures, a bus-mesh interconnection requires less routing area and power compared to a mesh interconnection. We also observed that the accumulated bandwidth requirement in the on-chip network to access off-chip data is much greater than bandwidth required to send neuron outputs between cores.

This study examines the design of several novel specialized multicore neural processors. Systems based on SRAM cores and memristor devices were examined. Detailed circuit simulations were used to ensure that the systems could be compared accurately. Two types of memristor cores were examined: digital and analog cores. Novel circuits were designed for both of these memristor systems. Additionally full system evaluation of multicore processors based on these cores and specialized routing circuits were developed. Our results show that the memristor systems yield the highest throughput and lowest power. We compared these specialized systems to more traditional HPC systems. Two commodity high performance processors were examined: a six core Intel Xeon processor, and an NVIDIA Tesla M2070 GPGPU. Care was taken to ensure the code on each platform was very efficient (multi-threaded on the Xeon processor, and a high device utilization CUDA program on the GPGPU). Our results indicate that the specialized systems can be between two to five orders more energy efficient compared to the traditional HPC systems. Additionally the specialized cores take up much less die area - allowing in some cases a reduction from 179 Xeon six-core processor chips to 1 memristor based multicore chip and a corresponding reduction in power from 17 kW down to 0.07 W.

This paper presents a segmented memristor crossbar array capable of performing pattern recognition tasks. Partial transistor isolation is used to segment smaller memristor crossbar structures. The synaptic density is less than that of a single large memristor crossbar, although this system is much more energy efficient. This system also reduces the amount of unwanted current paths that are a byproduct of large restive crossbar arrays. The proposed system is validated using SPICE simulations that utilize an accurate memristor model that we previously published. Additionally, wire resistance between memristor devices is accounted for to study how a realistic memristor circuit would perform in terms of energy, area, and ability to classify patterns. In this detailed implementation, the proposed system was shown to classify both 16 and 32 pixel images.

This paper presents a memristor SPICE model that is able to reproduce current-voltage relationships of previously published memristor devices. This SPICE model shows a stronger correlation to various published device data when compared to existing SPICE models. Furthermore, switching characteristics of published memristor devices with switching times in the nanosecond scale were modeled. Therefore, this model can be used to accurately simulate neural systems based on these high-speed memristors. This paper also demonstrates how this model can be used to accurately calculate switching energy of these high-speed devices, leading to more accurate power calculations in memristor based neural systems. Memristor crossbar circuits provide a potential method for developing very high density neural classifiers. This model was able to simulate crossbar circuits containing up to 256 memristors. It is significantly less likely to cause convergence errors when operating in the nanosecond switching regime with a large number of devices when compared with existing SPICE models.

Agent-based decision aids can improve their performance by mining domain knowledge captured in cognitive domain ontologies (CDOs). This paper introduces a cognitively enhanced complex event processing (CECEP) architecture to enable enhanced agent-based decision making. Additionally the paper examines the parallelization and acceleration of a key knowledge mining process within the architecture on high performance computing platforms. Speedups of almost a 1000 times were seen using 8 NVIDIA Tesla C2070 GPGPUs over 1 Xeon X5650 processor core. Speedups of this level will allow more complex knowledge domains to be searched in real time on reactive agents and thus enable systems with enhanced intelligence to be designed.

This paper presents a SPICE model for memristive devices. It builds on existing models and is correlated against several published device characterization data with an average error of 6.04%. When compared to existing alternatives, the proposed model can more accurately simulate a wide range of published memristors. The model is also tested in large circuits with up to 256 memristors, and was less likely to cause convergence errors when compared to other models. We show that the model can be used to study the impact of memristive device variation within a circuit. We examine the impact of nonuniformity in device state variable dynamics and conductivity on individual memristors as well as a four memristor read/write circuit. These studies show that the model can be used to predict how variation in a memristor wafer may impact circuit performance.

At present, a major initiative in the research community is investigating new ways of processing data that capture the efficiency of the human brain in hardware and software. This has resulted in increased interest and development of bio-inspired computing approaches in software and hardware. One such bio-inspired approach is Cellular Simultaneous Recurrent Networks (CSRNs). CSRNs have been demonstrated to be very useful in solving state transition type problems, such as maze traversals. Although powerful in image processing capabilities, CSRNs have high computational demands with increasing input problem size. In this work, we revisit the maze traversal problem to gain an understanding of the general processing of CSRNs. We use a 2.67 GHz Intel Xeon X5550 processor coupled with an NVIDIA Tesla C2050 general purpose graphical processing unit (GPGPU) to create several novel accelerated CSRN implementations as a means of overcoming the high computational cost. Additionally, we explore the use of decoupled extended Kalman filters in the CSRN training phase and find a significant reduction in runtime with negligible change in accuracy. We find in our results that we can achieve average speedups of 21.73 and 3.55 times for the training and testing phases respectively when compared to optimized C implementations. The main bottleneck in training performance was a matrix inversion computation. Therefore, we utilize several methods to reduce the effects of the matrix inversion computation.

The recently discovered memristor has the potential to be the building block of a high-density memory system. A memristor based crossbar memory system was analyzed in terms of timing and switching energy using SPICE. The memristor model in the simulations was designed to match the I-V characteristics of three different published devices. The simulation results for each device were compared to demonstrate the performance of a one transistor one memristor (1T1M) memristor crossbar.

A memristor based write circuit is presented that can update multiple memristors using a neuron spike generated by the Izhikevich model. A memristor read circuit is also presented that is capable of quantizing the resistance into 5 discrete values that could be digitally decoded. Together, these circuits provide the basic block for a memristor based neuromorphic architecture. The memristors were modeled using published device characterization data.

There is currently a strong push in the research community to develop biological scale implementations of neuron based vision models. Systems at this scale are computationally demanding and have generally utilized more accurate neuron models, such as the Izhikevich and Hodgkin- Huxley models, in favor of the integrate and fire model. This paper examines the feasibility of using a cluster of NVIDIA General Purpose Graphics Processing Units (GPGPUs) for accelerating a spiking neural network based character recognition network based on the Izhikevich and Hodgkin-Huxley models to enable such large scale systems. We utilized a 32 node cluster at NCSA containing an NVIDIA Tesla S1070 GPGPU on each node. Based on a thorough review of the literature, this is the first study examining the use of a cluster of GPGPUs for accelerating neuromorphic models. Our results show that the GPGPU can provide speedups of 24.6 and 177.0 times over a dual core 2.4 GHz AMD Opteron processor for the Izhikevich and Hodgkin-Huxley models respectively. Additionally, the MPI implementations of the models scaled almost linearly, with 16 GPGPUs providing throughputs of 14.1 and 15.9 times that of a single GPGPU for the Izhikevich and Hodgkin-Huxley models respectively. This indicates that clusters of GPGPUs are well suited for this application domain.

There is a significant interest in the research community to develop large scale, high performance implementations of neuromorphic models. These have the potential to provide significantly stronger information processing capabilities than current computing algorithms. In this paper we present the implementation of five neuromorphic models on a 50 TeraFLOPS 336 node Playstation 3 cluster at the Air Force Research Laboratory. The five models examined span two classes of neuromorphic algorithms: hierarchical Bayesian and spiking neural networks. Our results indicate that the models scale well on this cluster and can emulate between 108 to 1010 neurons. In particular, our study indicates that a cluster of Playstation 3s can provide an economical, yet powerful, platform for simulating large scale neuromorphic models.

As semiconductor devices have shrunk further into the nanoscale regime, a new device, the memristor, has been discovered that has the potential to transform neuromorphic computing systems. This device is considered as the fourth fundamental circuit element. It was first theorized by Dr. Leon Chua in 1971 and has been discovered by HP labs in 2008. This paper describes initial efforts at fabricating the memristor devices and examining their properties. Two versions of memristor devices have been fabricated at the University of Dayton and the Air Force Research Laboratory utilizing varying thicknesses of the TiO2dielectric layers. Our results show that the devices do exhibit the characteristic hysteresis loop in their I-V plots. Further refinement in the devices to achieve stronger hysteresis will be carried out as future work.

This paper presents the use of the Izhikevich and Hodgkin Huxley neuron models for image recognition. The former is more biologically accurate than the commonly used integrate and fire neuron model but has similar low computational requirements. Brain scale cortex models tend to use the more biological neuron models. The results of this work show that the Izhikevich model can be used for image recognition and would be a good candidate for a large scale visual cortex model. Neural networks based on these models are developed and applied to character recognition. They were able to identify 48 24times24 images and their noisy versions. The networks were accelerated using modern multicore processors and showed significant speedups. Such processors are likely to be used for developing high performance, large scale implementations of these image recognition networks.

There is a significant interest in the research community to develop large scale, high performance implementations of cortical models. These have the potential to provide significantly stronger information processing capabilities than current computing algorithms. At present we are investigating the implementation of six neuromorphic computational models on a large Sony PlayStation 3 cluster at the Air Force research lab. These six models span two classes of neuromorphic algorithms: hierarchical Bayesian and spiking neural networks. In this paper we have presented the performance gain of these six neuromorphic computational models for implementations on the cell multicore processor on the PlayStation 3. We show that the cell multicore architecture can provide significant performance gains for these models. We compare the performance gains of the two classes and see that the hierarchical Bayesian class provides higher speedups than the spiking network class in general. This is primarily due to the higher computational load per node in the former class. Our results indicate that the cell processor based PlayStation 3 would provide a good platform for the large scale implementation of the classes of neuromorphic models examined.

In this paper we study the acceleration of a new class of cognitive processing applications based on the structure of the neocortex. Our focus is on a model of the visual cortex used for image recognition developed by George and Hawkins. We propose techniques to accelerate the algorithm using reconfigurable logic, specifically a streaming memory architecture utilizing available off-chip memory. We discuss the design of a streaming memory access unit enabling a large number of processing elements to be placed on a single FPGA thus increasing throughput. We present an implementation of our approach on a Cray XD1 and discuss possible extension to further increase throughput. Our results indicate that using a two FPGA design with streaming memory gives a speedup of 71.9 times over a purely software implementation.

Advances in semiconductor technology enable larger processor design space, leading to increasingly complex systems. Designers must evaluate many architecture design points to achieve the optimal design. Currently, most architecture exploration is performed using cycle accurate simulators. Although accurate, these tools are slow, thus limiting a comprehensive design search. The vast design space of today's complex processors and time to market economic pressures motivate the need for faster architectural evaluation methods. This paper presents a superscalar processor performance model that enables rapid exploration of the architecture design space for superscalar processors. It supplements current design tools by quickly identifying promising areas for more thorough and time consuming exploration with traditional tools. The model estimates instruction throughput of a superscalar processor based on early architectural design parameters and application properties. It has been validated with the Simplescalar out-of-order simulator. The model, which executed 40,000 times faster, produces instruction throughput estimates that are with within 5.5% of the corresponding SimpleScalar values.

In this paper we study the acceleration of a new class of cognitive processing applications based on the structure of the neocortex. Specifically we examine the speedup of a visual cortex model for image recognition. We propose techniques to accelerate the application on general purpose processors and on reconfigurable logic. We present implementations of our approach on a Cray XD1 and compare the performance potential of scaling the design utilizing reconfigurable logic based acceleration to a software only design. Our results indicate that acceleration using reconfigurable logic can provide a significant speedup over a software only implementation.

On-chip interconnect demand is becoming the dominant factor in modern processor performance and must be estimated early in the design process. This paper presents a set of heterogeneous architectural models that combines architecture description and Rent's rule-based wiring models. These architecture models allow flexible heterogeneous system specifications, enabling investigations of prospective designs in different technology scenarios. Comparisons against actual data demonstrate the models' effectiveness for architecture explorations with highly accurate estimations of local and global wiring demand, as well as chip area and cycle time. Simulation of two candidate system designs reveal trends in interconnect delay with increasing architectural complexity, and confirm the need for high computational locality and short global wires for future architectures.