Reversible circuits are the essential building blocks of quantum computers and have zero energy dissipation. However, there is no general rule on how to synthesize an effective circuit with minimal cost. Many researchers have placed a high value on the design of algorithms for reversible circuit synthesis as it is the fundamental component to implement in many paradigms, such as Shor’s algorithm. In this paper, the knowledge navigated quantum-inspired tabu search algorithm (KNQTS) is proposed to synthesize several benchmark functions. KNQTS is a quantum-inspired algorithm with the concept of getting closer to the best solution and keeping away from the worst solution, and it has a great search ability. Furthermore, the proposed algorithm uses self-adaptive, global-best guided and Quantum-Not gate mechanisms to make all procedures more efficient and avoid sticking to the local optimum. This paper also compares the KNQTS approach’s experimental results with those obtained via other metaheuristics and previous algorithms. Finally, the result shows that the proposed KNQTS method outperforms other state-of-the-art methods and achieves the same functionality at a lower cost. The solutions are optimal or near-optimal.

To access sensitive information, some recent advanced attacks have been successful in exploiting implicit flows in a program in which sensitive data affects the control path and in turn affects other data. To track the sensitive data through implicit flows, several software and hardware based approaches have been proposed, but they suffer from the non-negligible performance overhead. In this paper, we propose a hardware tracking engine for implicit flow, called the implicit flow tracking unit (IFTU). By adopting the tracking scheme for implicit flow and mapping it to the specialized hardware, our solution can efficiently perform the implicit flow tracking with reasonable area costs.

We propose a software-hardware architecture, DataSafe, that realizes the concept of self-protecting data: data that is protected by a given policy whenever it is accessed by any application -- including unvetted third-party applications. Our architecture provides dynamic instantiations of secure data compartments (SDCs), with hardware monitoring of the information flows from the compartment using hardware policy tags associated with the data at runtime. Unbypassable hardware output control prevents confidential information from being leaked out. Unlike previous hardware information flow tracking systems, DataSafe software architecture bridges the semantic gap by supporting flexible, high-level software policies for the data, seamlessly translating these policies to efficient hardware tags at runtime. Applications need not be modified to interface to these software-hardware mechanisms. DataSafe architecture is designed to prevent illegitimate secondary dissemination of protected plaintext data by authorized recipients, to track and protect data derived from sensitive data, and to provide lifetime enforcement of the confidentiality policies associated with the sensitive data.

New security architectures are difficult to prototype and test at the design stage. Fine-grained monitoring of the interactions between hardware, the operating system and applications is required. We have designed and prototyped a testing framework, using virtualization, that can emulate the behavior of new hardware mechanisms in the virtual CPU and can perform a wide range of hardware and software attacks on the system under test.

Many applications require protection of secret or sensitive information, from sensor nodes and embedded applications to large distributed systems. The confidentiality of data can be protected by encryption using symmetric-key ciphers, and the integrity of the data can be ensured by using a cryptographic hash function to calculate a "digital fingerprint." In this paper, we propose reconfigurable FPGA hardware components that enable rapid deployment of cryptographic and other algorithms. The novelty of our hardware components is in their general-purpose design which enables easy mappings of algorithms to allow customizations of data protection for different usage scenarios. Since we utilize only a small part of an FPGA chip, our design can be readily integrated with other processing needs of a mobile device, a sensor node or a System-on-Chip. Important block ciphers like the Advanced Encryption Standard (AES) as well as advanced cryptographic hash algorithms like Whirlpool map well onto our general-purpose components. Our solution facilitates easy hardware implementation of customizable encryption and hashing solutions, with area and speed performance comparable to custom FPGA implementations targeted at a specific cipher or hash algorithm. We achieve the best efficiency in Mbps/slice for Whirlpool. Furthermore, the components that we have proposed can be used for many other applications - not just for implementing block ciphers and cryptographic hash functions.

This letter presents a novel steganography scheme capable of concealing a piece of critical information in a host message which is a binary image (e.g., a facsimile). A binary matrix and a weight matrix are used as secret keys to protect the hidden information. Given a host image of size m/spl times/n, the proposed scheme can conceal as many as /spl lfloor/log/sub 2/ (mn+1)/spl rfloor/ bits of data in the image by changing, at most, two bits in the host image. This scheme can provide a higher security, embed more information, and maintain a higher quality of the host image than available schemes.

In this paper we propose a new steganography scheme for hiding a piece of critical information in a host binary image (such as facsimiles). A secret key and a weight matrix are used to protect the hidden data. Given an image block of size m/spl times/n, our scheme can hide as many as [log/sub 2/(mn+1)] bits of data in the image by changing at most 2 bits in the image. This scheme, as compared to an existing scheme by M. Y. Wu et al. 1998), can provide higher security, embed more data, and maintain higher quality of the host image.