The RISC-V architecture has recently emerged as a popular open source option for the design of general purpose cores with a wide spectrum of operating specifications. In this paper, we present HAMSA-DI, a small footprint, energy-efficient, embedded RISC-V core, featuring a dynamically scheduled, in-order, dual-issue processing pipeline, supporting the popular Xpulp extensions. The proposed cost-effective dual-issue implementation provides a significant performance boost and improved energy-efficiency over baseline low-power cores under common benchmarks. These include a CoreMark score of 3.48 CM/MHz (+22%) and an Embench score of 1.3 (+13%) with certain benchmarks displaying as much as 22% less energy than the baseline CV32E40P core. The proposed design was fabricated as part of a 16nm test chip, running at 1GHz with an 0.8V supply voltage. Silicon measurements demonstrate that the proposed core can improve performance by as much as 8$\times $for programs operating with full dual-issue utilization with energy-efficiency improving by as much as 6.5$\times $, as compared to compiled code on a single-issue core.

Dynamic logic is a high-speed technology that was previously used in mature technologies, but lost popularity due to the increased leakage and process variations in advanced technologies. However, the recent popularity of circuits running in the cryogenic region provides a new opportunity for dynamic operation, thanks to the reduced leakages at such low temperatures. This paper revisits dynamic logic as a true candidate for high-performance and energy-efficient circuits for cryogenic operation in nanoscaled technologies. The paper first overviews and analyzes transistor operation at cryogenic temperatures and how it influences digital circuit design targeted to this regime. With these effects in mind, the use of dynamic logic families, including the classical dynamic (NORA) logic and the recently introduced Dual Mode Logic (DML) and Dual Mode Pass Logic (DMPL) families, are examined under cryogenic operation, showcasing improved performance and power efficiency. Measurements conducted on a 16 nm FinFET test chip validate their operation at low temperatures down to 4K, with supply voltages ranging 0.4–0.8-V. Furthermore, the considered dual mode logic families exhibit performance enhancements of up to 26% in dynamic mode and power efficiency increases up to 53% in static mode, compared to CMOS.

This work proposes a novel platform for bringing a project from the concept to the tapeout stage in a short amount of time. An open-source and extendable RISC-V architecture is exploited to build a small area footprint core. This leads the research platform to be flexible in terms of design integration, while also allowing fast design cycles of research chips.

Dual Mode Logic (DML) enables the dynamical operation of digital circuits optimized for energy-delay efficiency. Here, for the first time, DML is examined under cryogenic conditions, and its characteristics are evaluated for future applications. As a proof-of-concept, a DML testchip designed in 65nm technology was measured under cryogenic temperatures down to 4K. Measurements at supply voltages from 0.8V to 1.2V and temperatures ranging from 300K (room temperature) to 4K, confirm the effectiveness of DML under extreme temperatures.

This paper presents a hardware implementation of a digital watermarking system that can insert invisible, semifragile watermark information into compressed video streams in real time. The watermark embedding is processed in the discrete cosine transform domain. To achieve high performance, the proposed system architecture employs pipeline structure and uses parallelism. Hardware implementation using field programmable gate array has been done, and an experiment was carried out using a custom versatile breadboard for overall performance evaluation. Experimental results show that a hardware-based video authentication system using this watermarking technique features minimum video quality degradation and can withstand certain potential attacks, i.e., cover-up attacks, cropping, and segment removal on video sequences. Furthermore, the proposed hardware-based watermarking system features low power consumption, low cost implementation, high processing speed, and reliability.

A low power CMOS image sensor employing Adaptive Bulk Biasing Control (AB2C) approach is presented. The AB2C is a novel method that utilizes self adaptive biasing of the sensor array and digital periphery and allows sensor power reduction and image performance improvement. The presented AB2C technique can be easily implemented in a standard twin well or triple well CMOS technology. Both rolling shutter and global shutter imagers were examined using the AB2C, showing increased sensor output voltage swing, reduced in-pixel leakage currents, increased shutter efficiency and significant improvement in power dissipation of the scanning circuitry. A detailed description and analysis of the AB2C method is presented. Various image sensors employing AB2C have been implemented in a standard 0.18μm CMOS technology available through MOSIS and are operated via a 1.8V supply. Imagers operation is discussed and simulation results are reported.