A novel approach is presented for transforming a given scheduled and bound signal processing algorithm for a multiplexer based datapath to a BUS/RAM based FPGA datapath. A datapath model is introduced that allows maximum flexibility in scheduling bus transfers independent of operation scheduling. A novel integer linear programming (ILP) formulation that optimally selects and assigns data-transfers to busses while scheduling the bus transfers to minimize a linear combination of the number of busses, bus loading in terms of tristate drivers and fanout, registers and register file storage (RAM) locations. We demonstrate that our resulting optimal datapaths compare favorably to others for signal processing synthesis benchmarks such as: single and multiple elliptic filter and fast discrete-cosine-transform (FDCT).