A number of initiatives have begun to address the integration and test of core-based chip design. Several organizations, including an IEEE Test Technology Technical Committee (TTTC) and working groups of the Virtual Socket Interface Alliance (VSIA), meet regularly to consider standards and solutions. The most immediate issue that a chip designer must face is the integration of a core (or cores) into the chip. Three main approaches are popular. FIFO-based interfaces are quite common for VO interconnect cores; they have simple protocol rules and mate up well with DMA designs in the application logic. The core might instead mate to a microprocessor or I/O bus. For example, a multi-function chip can use an on-chip PCI bus to connect together multiple cores with PCI interfaces. The final common approach is a bus defined explicitly by an ASIC vendor or core provider to interconnect cores. For all three types of core interconnection, handling functional operation is only half of the solution. As with all semiconductor devices, a core-based chip must be well tested in production to become a viable product.

Attempts to link design and test are discussed. They are shown to have some value and all have been employed successfully by many engineers in both domains. A "wish list" is presented which summarizes some ways to make this process easier: (1) Test engineers need to be involved in simulation. (2) ATPG tools must evolve to support path delay testing and other techniques that leverage static timing analysis. (3) More effective use should be made of BIST approaches. (4) Finally, it would be nice if testers always had enough memory so that test engineers didn't have to deal with RTZ signals and the like. A more direct mapping from simulation to the tester would be the result.

Concert is a shared-memory multiprocessor testbed intended to facilitate experimentation with parallel programs and programming languages. It consists of up to eight clusters, with 4-8 processors in each cluster. The processors in each cluster communicate using a shared bus, but each processor also has a private path to some memory. The novel feature of Concert is the RingBus , a segmented bus in the shape of a ring that permits communication between clusters at relatively low cost. Efficient arbitration among requests to use the RingBus is a major challenge, which is met by a novel hardware organization, the criss-cross arbiter . Simulation of the Concert RingBus and arbiter show their performance to lie between that of a crossbar switch and a simple shared intercluster bus.