Modern trends towards higher architectural complexity and smaller technology nodes do not align with the requirement for reliability that many application domains expose. While system robustness remains one of the most critical aspects for missioncritical application domains, the currently available tools allow designers to accurately investigate the reliability only at the late design stages, limiting the effectiveness of their intervention in addressing architectural vulnerabilities.In this context, this paper presents a novel framework for early-stage reliability assessment that enables fast evaluations to guide the RTL design process, without compromising analysis quality or relying on imprecise high-level fault injection models. In the presented analysis, the paper shows how the proposed framework leads to a significant time saving when targeting highly parametric hardware designs, achieving up to 79 x compile time reduction, and up to $37.6 x$ simulation time reduction when compared to other state-of-the-art approaches.

The growing demand for deployment of Artificial Intelligence (AI) on resource-constrained edge devices has motivated extensive research on the design of efficient edge-compatible AI hardware accelerators. One of the most promising solutions are the self-adaptive AI accelerators, capable of optimizing in real time their performance and energy consumption according to application requirements. This work introduces the EU-funded project Twinning for Excellence in Adaptive Edge Artificial Intelligence (AIDA4Edge), aimed to advance the state-of-the-art in the design of adaptive neural network accelerators for edge applications. The main goal is to develop a novel hybrid self-adaptive neural network architecture combining spiking and artificial neural networks, and supporting runtime adaptation of network functionality, precision and reliability. Furthermore, we aim to enhance the neural network training by incorporating hardware and quantization constraints in an automated tuning engine.

Abstract In the design of integrated circuits, one critical metric is the maximum delay introduced by combinational modules within the circuit. This delay is crucial because it represents the time required to perform a computation: in an Arithmetic Logic Unit, it represents the maximum time taken by the circuit to perform an arithmetic operation. When such a circuit is part of a larger, synchronous system, like a CPU, the maximum delay directly impacts the maximum clock frequency of the entire system. Typically, hardware designers use static timing analysis to compute an upper bound of the maximum delay because it can be determined in polynomial time. However, relying on this upper bound can lead to suboptimal processor speeds, thereby missing performance opportunities. In this work, we tackle the challenging task of computing the actual maximum delay, rather than an approximate value. Since the problem is computationally hard, we model it in answer set programming (ASP), a logic language featuring extremely efficient solvers. We propose non-trivial encodings of the problem into ASP. Experimental results show that ASP is a viable solution to address complex problems in hardware design.

Investigating the effects of Single Event Upset in domain-specific accelerators represents one of the key enablers to deploy Deep Neural Networks (DNNs) in mission-critical edge applications. Currently, reliability analyses related to DNNs mainly focus either on the DNNs model, at application level, or on the hardware accelerator, at architecture level. This paper presents a systematic cross-layer reliability analysis of NVIDIA Deep-Learning Accelerator, a popular family of industry-grade, open and free DNN accelerators. The goals are i) to analyze the propagation of faults from the hardware to the application level, and ii) to compare different architectural configurations. Our investigation delivers new insights into the performance-accuracy-reliability trade-off spanned by the configuration space of Deep Learning accelerators. In particular, the Failure in Time can be reduced up to 4.3x for the same DNN model accuracy and by up to 9.4x for the same performance, while accounting 6.5x inference latency and 1.1% accuracy drop, respectively.

Deep learning accelerator models described with software imperative languages are frequently used for their large-scale reliability analysis in order to overcome the prohibitive simulation times of logic-level and RTL models. However, they are faced with the challenge of preserving consistency between software-visible variables and faulty microarchitectural states. The goal of this work is to determine a suitable accelerator modelling that enables analysis without overloading the simulation engine. Toward this goal, the paper explores different accelerator modelling strategies featuring increasing levels of hardware visibility. They are compared in their capability to gain insights into the reliability of the multiply-and-accumulate (MAC) pipeline of an industry-standard deep learning accelerator from NVIDIA. Our results show that subtle microarchitectural details that are typically overlooked by competing approaches play a relevant role in determining accelerator reliability.

Emerging nanotechnonologies such as ambipolar carbon nanotube field effect transistors (CNTFETs) and silicon nanowire FETs (SiNFETs) provide ambipolar devices allowing the design of more complex logic primitives than those found in today's typical CMOS libraries. When switching, such devices show a behavior not seen in simpler CMOS and FinFET cells, making unsuitable the existing delay fault testing approaches. We provide a Boolean model of switching ambipolar devices to support delay fault testing of logic cells based on such devices both in Boolean and Pseudo-Boolean satisfiability engines.

Most multi- and many-core integrated systems are currently designed by following a globally asynchronous locally synchronous paradigm. Asynchronous interconnection networks are promising candidates to interconnect IP cores operating at potentially different frequencies. Nevertheless, post-fabrication testing is a big challenge to bring asynchronous NoCs to the market due to a lack of testing methodologies and support for them. In particular, the unpredictable delay variability introduced by the manufacturing process may differentiate the delay of nominally-balanced I/O timing paths, thus making the order of the input patterns unpredictable and precluding the correct behaviour of signature-based test compactors. This paper tackles this challenge by proposing a testing framework for asynchronous NoCs which works effectively despite delay variations in and across timing paths of the NoC under test. Moreover, in order to mitigate the growing test application costs in modern ICs, we come up with a built-in self-testing infrastructure which automatically controls and delivers the outcome of the testing process without the intervention of an external automatic test equipment (ATE).

Feedback bridging faults may give rise to oscillations within integrated circuits. This work mainly investigates the propagation of oscillations, a behavior that may have a relevant impact on the fault detection. We propose both a logic-level model of the faulty circuit and two techniques aiming to the generation of high-quality test sequences.

Networks-on-chip need to survive to manufacturing faults in order to sustain yield. An effective testing and configuration strategy however implies two opposite requirements. One one hand, a fast and scalable built-in self-testing and self-diagnosis procedure has to be carried out concurrently at NoC switches. On the other hand, programming the NoC routing mechanism to go around faulty links and switches can be optimally performed by a centralized controller with global network visibility. To the best of our knowledge, this article proposes for the first time a global network testing and configuration strategy that meets the opposite requirements by means of a fault-tolerant dual network architecture and a fast configuration algorithm for the most common failure patterns. Experimental results report an area overhead as low as 12.5% with respect to the baseline switch architecture while achieving a high degree of fault tolerance. In fact, even when multiple stuck-at faults are considered, the capability of fault masking by the dual network is always over 80%, and the support for multiple link failures is more than 90% in presence of two unusable links in the main network with minimum set-up times.

This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network (NoC). Concurrent BIST operations are carried out after reset at each switch, thus resulting in scalable test application time with network size. The key principle consists of exploiting the inherent structural redundancy of the NoC architecture in a cooperative way, thus detecting faults in test pattern generators too. At-speed testing of stuck-at faults can be performed in less than 1200 cycles regardless of their size, with an hardware overhead of less than 11%.

Networks-on-chip need to survive to manufacturing faults in order to sustain yield. An effective testing and configuration strategy however implies two opposite requirements. On one hand, a fast and scalable built-in self-testing and self-diagnosis procedure has to be carried out concurrently at NoC switches. On the other hand, programming the NoC routing mechanism to go around faulty links and switches can be optimally performed by a centralized controller with global network visibility. This paper proposes a global hardware infrastructure that meets such requirements by means of a fault-tolerant dual network architecture and a configuration strategy for reprogramming the routing mechanism of each switch. This is the first complete infrastructure for testing and reconfiguring a NoC based on reprogrammable routing logic.

This letter addresses the problem of delay fault test generation in circuits using macros whose implementation is not known. The proposed approach uses a new signal representation that allows us to evaluate any kind of sensitization conditions (robust, non-robust, and functional) by means of Boolean differential calculus. Such an approach makes use of binary decision diagrams to support the computation of sensitization conditions for each macro along a path and of Boolean satisfiability to justify such conditions at primary inputs. Results are shown for a set of benchmarks.

This paper addresses the problems related to resistive opens and bridging faults that lie out of the most critical paths. These faults cannot be detected by traditional delay fault testing because the induced delay defects are not large enough to result in timing violations when the test rate is equal to the nominal operating frequency. In spite of this problem, resistive opens and bridgings should be detected because they may give rise to reliability problems. To detect them, we propose a testing method that is based on the propagation of pulses within the faulty circuit and that exploits the degraded capability of faulty paths to propagate pulses. The effectiveness of our method is analyzed at the transistor level and compared with the use of reduced clock periods to detect the same class of faults. Results show similar performance in the case of resistive opens and better performance in the case of bridgings. Moreover, the proposed approach is not affected by possible problems in the clock distribution.

This paper analyzes the problem of timing related common mode failures in redundant systems. The specific case of duplex systems in the presence of delay faults is analyzed by providing a probabilistic characterization of undetectable errors. PDF simulation was used to evaluate the probability of undetectable errors in conventional duplex systems and in duplex systems making use of a simple kind of data diversity.

A fuzzy model is proposed to analyze the effectiveness of test pairs targeting path delay faults. This model is accurate enough to rank nonrobust tests by accounting for conditions not considered in existing models. It remains fully consistent with the traditional test robustness analysis. Finally, it also provides a coverage metric to be used to rank whole test sets. The proposed model has been implemented in a logic level path delay fault simulator. Its accuracy has been validated, for a set of combinational benchmarks, by means of a Monte Carlo logic-level event-driven path delay fault simulator.

In high reliability systems, the effectiveness of fault tolerant techniques, such as Triple-Modular-Redundancy (TMR), must be validated with respect to the faults that are likely in the current technology. In todays' Integrated Circuits (IC), this is the case of crosstalks, whose importance is growing because of device & interconnect scaling. This paper analyzes the problem of crosstalk faults at the inputs of voters in TMR systems. In particular, possible problems are illustrated, and it is shown that such crosstalk may invalidate the reliability of both voting, and diagnosing operations. The problem is analyzed from a probabilistic point of view. Its occurrence is estimated by using a set of TMR systems obtained with combinational benchmarks as functional modules. The possible problems of such operations are discussed in the presence of crosstalk faults. It is shown that crosstalk may invalidate the reliability of both voting, and diagnosis operations. A probabilistic model of the voting & diagnosis operations in the presence of crosstalk has been developed. Finally, such a model has been used to estimate the probability of voting & diagnosis failures in a set of TMR systems obtained by using combinational benchmarks as functional modules. We have shown that the presence of crosstalk faults at voter inputs may impair both the voting, and the diagnosis mechanisms. This problem has been quantified by applying a probabilistic model of crosstalk fault effects on voting and diagnosis to a set of benchmark circuits. Results show that crosstalk may create a reliability problem for TMR systems. Such a problem can be solved by using on-line testing or design for testability providing additional controllability & observability to the replicated functional units.

We propose a methodology for the concurrent detection of power supply noise affecting a general synchronous system and exceeding a tolerance bound to be chosen according to the system's constraints. Our solution is based on a suitable self-checking scheme which concurrently monitors a signal of the system clock distribution network and which is, by design, able to provide an output error message upon the occurrence of power supply noise. The produced error indication can then be exploited to recover from the detected noise (thus guaranteeing system's correct operation), or to accomplish diagnosis. Our scheme negligibly impacts system's performance, features self-checking ability with respect to a wide set of possible internal faults and keeps on revealing concurrently the occurrence of power supply noise, despite the possible presence of noise affecting also ground.

Summary form only given. Weighted pseudorandom test generation (WPRTG) uses test sequences characterized by non-uniform distributions of test vectors in order to increase the detection probability of random resistant faults. Such non-uniform distributions are characterized by the values of signal probability of the CUT inputs (weights). Since different faults may require different distributions, a (small) number of distributions is typically used. The weights of such distributions are identified by analyzing the CUT The corresponding pseudorandom sequences are typically obtained by inserting a combinational network between the TPG and the CUT. Differently from the genetic-based approaches, where only numerical coefficients are computed, we have used an evolutionary programming (EP) algorithm that directly evolves the WGU network. In fact, evolutionary approaches have been shown to be effective in the design of digital circuits. In particular, we evolve a population were each individual represents a possible WGU and the fitness function considers the fault coverage as a primary target and the test length and the cost of the WGU as secondary ones. The fault coverage is evaluated here by means of fault simulation.

In this work, the problem of open faults affecting the interconnections of SC circuits composed by data-path and control is analyzed. In particular it is shown that, in case opens affect control signals, some problems may arise even if both control and data-path signals are concurrently checked. In particular, wrong codewords may be generated at the outputs of multiplexers and registers. To address this problem, new registers and multiplexers are proposed which allow the design data-paths which are TSC with respect to opens (and resistive opens). These components are also TSC with respect to stuck-at, transistor and gross delay faults. They present a good testability with respect to resistive bridgings.

We propose a self-checking scheme for the on-line testing of power supply noise, exceeding a tolerance bound, to be chosen according to system constraints. Upon the occurrence of such a noise, our scheme provides an output error message, which can be exploited for diagnostic purposes or to recover from the detected noise (thus guaranteeing correct system operation). As far as we are aware, no on-line testing scheme for power supply noise has been proposed up to now. Our scheme has negligible impact upon system performance, features a self-checking ability (with respect to a wide set of possible internal faults) and reveals, on-line, the occurrence of power supply noise, despite the possible presence of noise affecting ground.

Testing bridging faults in deep submicron CMOS digital ICs faces new problems because of pushing the technology limits. The growing dispersion of process parameters makes it hard to use conventional bridging fault models for high-quality testing. A new fault model is proposed to account for bridging faults in a way that is independent of electrical parameters and provides a significant coverage metric. Conditions are defined to ensure that (under steady-state conditions) either a fault is detected by a test sequence or it will not give rise to errors for any other input, independently of the actual values of IC parameters. Such a fault model has been implemented in a simulator and validated over combinational benchmarks.

This work applies weight based codes to the detection of crosstalk originated errors. This type of fault, whose importance grows with device scaling may originate errors that are undetectable by the commonly used error detecting codes in VLSI ICs. Conversely, such errors can be easily detected by weight based codes that, however, have smaller encoding capabilities. In order to reduce the cost of these codes, a graph theoretic optimization is used. Moreover new applications of these codes are explored regarding the synthesis of self-checking FSMs, and the detection of errors related to the clock distribution network.

Fault simulation and testability analysis are major concerns in design flows employing intellectual-property (IP) protected virtual components. In this paper we propose a paradigm for the fault simulation of IP-based designs that enables testability analysis without requiring IP disclosure, implemented within the JavaCAD framework for distributed design. As a proof of concept, stuck-at fault simulation has been performed for combinational circuits containing virtual components.

Summary form only given. This paper presents a self-checking, on-line testing and diagnosis scheme for bus lines affected by intermediate voltage values possibly due to bridging faults, or to different kinds of faults affecting the bus connected units.

We present a self-checking detection and diagnosis scheme for transient, delay, and crosstalk faults affecting bus lines of synchronous systems. Faults that are likely to result in the connected logic sampling incorrect bus data are on-line detected. The position of the affected line(s) within the considered bus is identified and properly encoded. The proposed scheme is self-checking with respect to a realistic set of possible internal faults, including node stuck-ats, transistor stuck-ons, transistor stuck-opens, resistive bridgings, transient faults, delays and crosstalks.

The reliability of a fault-tolerant circuit may be drastically impaired by the presence of maskable faults that never affect its functionality. Design for testability (DFT) techniques have to be applied to make maskable faults detectable. During the testing phase, traditional DFT schemes inhibit fault masking and/or activate additional observation/control paths through the circuit. Such schemes, however, do not enable on-line testing and cannot be applied to multilevel fault-tolerant circuits, where fault-masking is repeatedly performed inside the circuit. We propose a new approach to the design of testable fault-tolerant CMOS circuits that overcomes both limitations. Our approach is based on the use of I/sub DDQ/-checkable voters (ICVs) that enable a complete test of maskable faults of any multiplicity during normal operations.

This paper investigates the application of Shannon (BDD) circuits, that feature interesting low-power capabilities, to the design of self-checking functional units. A technique is proposed that, by using a time redundancy approach, makes this kind of circuits totally self-checking with respect to stuck-at-faults. For a set of possibly used pass-transistor-based CMOS implementations, we show that the totally self-checking or the strongly fault secure properties hold for a wider set of realistic faults, including transistors stuck-open/on and bridgings.

This paper analyses some of the most common error-detecting codes used in self-checking circuits with respect to the errors induced by crosstalk faults (CFs). The electrical-level behavior of circuits in the presence of CFs has been analyzed by considering these faults as parametric. A logic-level model providing the probability of errors has been abstracted and applied to the case of functional unit outputs (buses). Finally, the probability of detectable and undetectable errors has been evaluated for the parity, two-rail, m-out-of-n, and Berger codes, thus providing some design hint.

This paper presents a novel 1-out-of-n checker that, compared to the other implementations up to now presented, features the advantages of: (i) satisfying the TSC or SCD property with respect to all possible internal faults representative of realistic failures; (ii) presenting a single output line; (iii) requiring significantly lower area overhead.

This paper analyses the problem of systems' on-line testing with respect to logic errors due to crosstalk, delay and transient faults. In particular we show that logic errors due to crosstalk noise between internal, adjacent lines may not be on-line detectable by conventional concurrent error detection techniques using error detecting codes. Hence, a detector is proposed that allows the on-line detection of such logic errors, and that is self-checking with respect to a wide set of possible internal faults representative of realistic failures, including crosstalk, delay, and transient faults.

This paper proposes an on-line testing scheme for permanent and temporary faults which affect signals of the clock distribution network of synchronous systems, and which make them stuck-at, or change with incorrect frequency or duty-cycle. By means of straightforward modifications, the proposed scheme can be also used to detect on-line undesired skews between couples of clock signals.

In this paper a single output self-checking n-input comparator is presented. The proposed circuit, which can be used as n-variable two-rail checker or as equality checker features a compact structure, is Totally-Self-Checking or Strongly Code-Disjoint with respect to a wide set of realistic faults, and requires a limited set of input code words for fault detection (thus it can be used to implement also embedded comparators).

At different design levels, testability is becoming more and more important since high levels of reliability are required by many applications. In this work, a novel approach to the mapping between signal lines and gate inputs is proposed, targeting the I/sub DDQ/ testability of internal faults. Suggesting an additional cost function for the routing process, the method provides significant testability enhancements without affecting either the gate-level structure of the circuit or the internal layout of the gates, as proved with regards to bridging faults.

This paper investigates the detection of parametric bridging and delay faults affecting the functional block of CMOS self-checking circuits (SCCs). As far as these faults are concerned, classical definitions are shown to become ambiguous because they are entirely based on logic considerations. Thus, new definitions are proposed here to consider the analog and dynamic effects of such faults, and to ensure that they do not produce any problem at the system level. Moreover, electrical level design rules aimed at satisfying these conditions are proposed for self-checking circuits with combinational functional blocks. The problem of their practicability and effectiveness is analyzed in detail, and is shown by means of significant examples.

This paper addresses the problem of the design of embedded two-rail checkers. In particular a simple additional circuit is proposed which can be used to make a two-rail checker receive all the codewords of the two-rail code, independently of which and how many codewords are produced by its driving functional block or checkers. The proposed circuit features a high online self-testing ability with respect to possible internal faults and a compact structure.

This paper presents a fault model, called node-break fault model, to effectively account for broken connections inside CMOS circuits. The proposed model is very general since it allows to generate test vectors for broken connections that cannot be detected by means of test sequences for stuck-open faults. In addition, the detection of a broken connection in a node ensures the detection of all stuck-open faults of the transistors connected to that node, thus superseding the stuck-open fault model. The model can be used to derive tests and to perform fault simulations independent of the actual layout of the circuit. Conditions for the detection of broken connections are derived from electrical considerations (aimed at verifying the presence of electrical continuity between the terminals of transistors connected to a node) while the minimum number of input vectors to test for broken connections in a node is determined by graph theory. Fault simulations performed on benchmark circuits using test sequences oriented to the detection of stuck-open faults show their inadequacy in detecting node-break faults, thus claiming for considering such a fault model in the test pattern generation.

A sensing circuit for on-line testing of delay faults is presented. It can be used to monitor the outputs of circuits that are either general, or designed to be self-checking with respect to steady-state errors. Detailed analyses of the proposed circuit have shown that it is preferable to alternate solutions from the point of view of both the accuracy and the self-testing capability that make it suitable for self-checking applications. Checking architectures for delay faults, making use of the proposed sensing circuit and of standard checkers, are presented.

So far, the test pattern generation for I/sub DDQ/ testing has been performed without considering the value of the faulty current in comparison with the minimum current that is detectable as a fault: this approach will be shown to be misleading, since it actually gives optimistic coverage evaluation. Then, this work presents an ATPG strategy that targets the highest valves of current during the fault activation, in such a way that either a higher fault coverage can be obtained or a less accurate sensor can be used.

This paper presents a study of the dynamic behavior of CMOS and BiCMOS digital circuits induced by bridging faults, whose resistance value is shown to have a strong impact on the dynamic behavior of faulty gates and of their fan-out gates. The problem of fault detection is addressed considering delay fault testing and results are compared with those achieved by means of functional testing. Electrical simulation has been used to investigate the main differences between BiCMOS and CMOS circuits. It is shown that, because of the large driving capability of BJTs, the detection as delay faults of bridging faults in BiCMOS circuits is more difficult than in the CMOS case.>

The authors point out that the simulation of resistive bridging faults inside complex CMOS macrogates requires proper evaluation of resistances, in order to correctly determine realistic fault coverages. Here, an approach applicable to a large category of faults (bridgings, transistor stuck-ons, and node stuck-ats) that give rise to resistive paths between power supply and ground, and hence are all covered by the general term 'bridging faults,' is presented. This method, which avoids the single-fault-injection procedure, fault analysis is performed inside the macrogates aimed to determine the threshold resistance, thus discriminating whether or not a given fault is detectable as a logic error. This analysis is performed inside CMOS macro-gates whose output is observable. To fully characterize the quality of a test sequence with regard to resistive bridging faults, a new definition of fault coverage is presented, because the common concept of fault detection is not applicable to parametric faults.>

This paper presents a study of the effects on the electrical behavior of BiCMOS digital circuits induced by bridging faults, whose resistance value is shown to have a strong impact on the static and dynamic behavior of faulty gates and of their fan-out gates. The problem of fault detection is addressed considering different testing techniques (current monitoring, functional, and delay testing). Electrical simulation has been used to investigate the main differences between BiCMOS and CMOS circuits. It is shown that, because of the large driving capability of BJTs, the detection of bridging faults in BiCMOS circuits is more difficult than in the CMOS case when functional or delay testing is used whereas it becomes more effective when adopting current monitoring.>

This paper presents a new approach to the fault simulation of parametric bridgings in CMOS ICs synthesized by means of libraries of macro-gates. The method is based on a fast but accurate preliminary characterization of any macro-gate for each input set. Such a characterization provides all information to determine, during the actual fault simulation, the maximum value of resistance for any considered bridging that makes the fault observable at a circuit primary output. This library characterization is very general, and can be used with any fa.ult simulation technique. Results on several benchmarks show that this approach allows the fault simulation of internal parametric bridging faults in a time comparable to that of the classical line stuck-ats.

This paper analyzes the effects induced on the electrical behavior of BiCMOS digital circuits by bridging faults, whose instrinsic resistance value is shown to have a strong impact on the static behavior of faulty gates and of their fan-out gates. The problem of fault detection is then addressed considering two different testing techniques (current monitoring and functional testing). Simulations of the electrical behavior of faulty BiCMOS circuits have enlightened the main differences with respect to the CMOS technology: the larger driving capability of BJTs with respect to MOSFETs makes the detection of bridging faults much more difficult in BiCMOS circuits when functional testing is considered, but more effective when current monitoring is used.

The authors present two methods for computing the fault detection probabilities in combinational networks. The methods provide a deeper insight into the effects of signal correlations caused by multiple fan-out reconvergencies and can be used in testability analysis to predict the fault coverage of pseudorandom patterns. The performances of these algorithms have been tested on significant benchmarks and compare favorably with those of previous procedures.>

A probabilistic approach to the detection of analog faults (i.e. transistors stuck-on and bridgings) in CMOS circuits that depends on the conductances of faulty and fault-free networks is presented. It is shown that unrealistic fault coverages can be obtained by simply assigning constant values to the conductances of transistors and bridgings and by comparing the resultant conductances of faulty and fault-free conflicting networks. To solve this problem, all conductances are considered as random variables with normal distribution. Conductance distributions of complex conflicting networks can be easily evaluated, and the detection probability of each fault is determined. The expected coverage of analog faults is known at the end of a fault simulation. This result is shown to be more realistic than those obtained in a deterministic way. Fault coverages of analog faults obtained by means of a gate-level fault simulator are discussed for a complex FCMOS benchmark.>

The authors present a novel technique to study the detection of non-stuck-at faults in CMOS circuits. Gate-level models of CMOS faults not yet adequately covered in the literature are developed. Suitable models for transistor stuck-open and stuck-on, gate-drain shorts, and bridgings are implemented in a fault simulator. Results obtained with typical circuits are presented and discussed to analyze the influence of circuit architecture and type of test vector (deterministic or pseudorandom) on the coverage of non-stuck-at faults. The following general conclusions are drawn from these results: (1) shorts between transistor gate and drain are adequately detected by stuck-at oriented test patterns, and, hence, they do not represent a significant problem in IC testing: (2) the coverage of transistors stuck-open is significantly dependent on the test pattern generation method used; (3) the detectability of bridgings depends strongly on the circuit topology; and (4) the indirect coverage of transistors stuck-on is inadequate, essentially because a large number of them are undetectable.>

A novel fault grading heuristic is presented, based on the critical path tracing technique that tackles the problems associated with fan-out reconverging nodes (FORNs) without using forward propagation of the fault effects. To determine the criticality status of a fan-out reconverging node, which can differ from that of its fan-out branches (FOBs), the concepts of evidencing and masking paths are used. Using the statistics from exact fault simulations, heuristic rules are derived for the generation of masking and evidencing paths. The results obtained on benchmark circuits show good accuracy for fault coverage estimates and a computation time linear in the number of gates and comparable to that of the fault-free simulation.>

An investigation of the properties of multiple input shift registers for signature analysis is presented. The assumption of independent errors at the register inputs has been used to model the register behavior as a Markov process whose equations have been solved to obtain the exact dependence of aliasing probabilities as a function of test length, input error probabilities, and feedback structure. Some unique featured of maximum-length registers are proven. Accurate simplified expressions of aliasing probability are derived for use as tools in the evaluation of the coverage.>

Two methods for the calculation of fault detection probabilities in combinational networks are presented. These methods provide a better accuracy than existing algorithms and a deeper insight into the effects of first order correlations to multiple fan-out reconvergencies. These techniques have been applied to standard benchmarks as well as to a few commercial circuits and have shown to provide a significant improvement compared with existing methods with minimal drawbacks in terms of required computing resources.>

Novel design-for-testability schemes are suggested to improve the detectability of transistor stuck-on faults, bridgings, and gate oxide shorts in CMOS digital circuits, with limited extra hardware and minimum degradation of circuit performance. One of the techniques makes analog faults detectable by observing the circuit outputs just as for stuck-ats. Also described is a technique in which the gates are modified with the insertion of n-channel FETs whose drains are the input of a ratioed NOR testing logic realized with n-channel drivers and a single resistive p-channel pull-up device.>

The Markov chain model of linear feedback shift-registers (LFSRs) for signature analysis testing is analytically solved to obtain the exact expression of the aliasing error probability as a function of test length, error probability, and the structure of the feedback network. The dependence on feedback configuration is explored in depth, and it is proven that maximum-length LFSRs have the best performances with respect to aliasing, regardless of the particular structure of their feedback network. Simplified expressions of aliasing probability are also derived for use as practical tools to design LFSRs for IC signature analysis testing, and a heuristic criterion is given for the identification of peaks in aliasing probability.>

The authors present an accurate model of aliasing probability in signature analysis testing, based on the assumption of independent error bits, that makes it possible to treat the statistical behavior of the register as a Markov process. A proof is given that minimum-hardware registers realizing maximal counting sequences represent optimal choices for aliasing minimization. Exact as well as simplified expressions of aliasing probability have been derived, and a criterion for the identification of maximal aliasing conditions is presented to be used as a tool for the choice of optimal test length.>