In this paper, a method is proposed to accurately estimate the power yield, considering process-induced temperature and supply voltage variations. Process variations impose statistical behavior on the temperature and leakage current. This, in turn, impacts the IR drops due to the variations in the current, drawn off the power grid. By considering the process-induced statistical profile of the temperature and Vdd, the power yield is estimated for a chip. This helps check the robustness of the circuits early in the design process. The experimental results on the ISCAS89 benchmarks indicate a significant yield loss, if the statistical measures of the temperature and voltage drop are ignored. Monte Carlo simulations verify the accuracy of the developed methodology.

Parametric yield loss has become a significant issue in the design of nanometer integrated circuits (IC). In this paper, the impact of supply (Vdd) and threshold voltage (Vth) variations on the yield loss for the current and future CMOS technologies is investigated. The results demonstrate that, despite the temporary improvement due to the use of high-k dielectric materials and metal gates (HiK+MG), parametric yield and design robustness will remain amongst the major challenges in the future technology generations. Subsequently, design centers in the Vth-Vddplane are suggested for having more robust and reliable circuits for the nodes. Monte-Carlo simulations using SPECTRE and HSPICE verify the provided results in this work for 90nm to 16nm nodes.

Variations in supply (Vdd) and threshold voltages (Vth) significantly impact parametric yield. These variations also affectVddandVthscaling, two power reduction techniques that effectively reduce dynamic and static power consumption. This paper presents a statistical methodology for maximizing yield and optimizing supply and threshold voltage scaling under theVddandVthvariations. A design-specific feasible region is constrained by a minimum performance and maximum temperature in theVth-Vddplane. A tolerance box is placed in the feasible region so that its center provides the nominal values forVddandVthsuch that the design has a maximum immunity to the variations and maximizes the yield for the given constraints. It is demonstrated that the location of the tolerance box and, therefore, the values ofVddandVthdepend on the design metrics, circuit switching activity, transistor sizing, and the given constraints. Monte Carlo simulations indicate a 25% increase in the yield for 90-nm CMOS technology. In addition, the methodology can be adopted as a variability-aware guideline in a design specific power and performance optimization and is applicable to both continuous and discrete voltage scaling. SPECTRE simulations verify the developed method.