For the original article see ibid., vol.9, no.10, p.1028-46 (1990). In the above-titled paper A.J. Al-Khalili et al. claim that the expression derived by the commenters (1987) for the short-circuit energy dissipation per transition for a CMOS inverter while the n-channel transistor is discharging the load capacitor is not correct, and they suggest that some mistakes were made during the integration. The commenters point out that a rederivation showed that their expression is correct, and even if it is given for equal p- and n-channel transistors, it can easily be generalized to arbitrary p- and n-channel transistor sizes.>

The halo algorithm, a new and efficient hierarchical algorithm for corner-based design rule checking, is presented. The basic idea is to check each cell in its context by first identifying all elements that interact with the cell, thereby completely eliminating the rechecks of the traditional hierarchical methods. Identical interactions, repeated at several instances of a cell, are identified and checked as one interaction. The concept of the inverse layout tree is introduced to handle the interacting primitives. No restrictions are enforced on the hierarchical structure of the layout, and error messages are placed in the cells where the errors should be corrected. Performance is exemplified using several test-circuits. It is shown that the halo algorithm offers a five to twentyfold speed increase when the hierarchical circuit description is verified instead of a flattened description.>

A structured method for geometric design rule definitions is presented in terms of edge-based constraints. Using this approach, intralayer design rules such as width and spacing of single layers, and interlayer design rules such as clearance, margin, extension, and overlap of two different layers can be specified in terms of two high-level design rule macros only. The tedious and complicated task of specifying detailed design rules in the technology file is thereby eliminated and placed by a simple macro rule file giving a much better overview of the design rules. Efficient rule compilers have been developed to expand these macro descriptions of the design rules onto basic checks for Magic and for corner-based design rule checking. As an example, the MOSIS scalable CMOS design rule set can be described in terms of the two design rule macros only. More complicated design rules, such as conditional and conjunctive design rules, are also discussed.>

The inverse layout tree concept is used to perform fully hierarchical DRC without any constraints on the use of overlapping or incomplete cells that are completed at higher levels of hierarchy. Hierarchy is preserved and design rule violations are displayed in the cell where they should be corrected. The DRC is corner-based and processes 200-800 corners/second on a VAX 11/750.

The authors present the inverse layout tree as a means of performing fully hierarchical design verification without any restrictions on subcell overlaps. This provides a fast and general method of marking design rule errors or extracted devices at the correct hierarchical level. The inverse layout tree for each element is built up as layout data is processed from the bottom up. When layout processing is completed one can go through the layout again and use the inverse layout trees to determine the most appropriate cell for each element. New elements formed as layout from different cells overlap can now be placed at the lowest level of hierarchy where they always appear instead of being indiscriminately incorporated in the parent cell. The method preserves the original hierarchy to the greatest possible extent. The method has been implemented in the corner-based design-rule checker and circuit extractor, Corny. As an important example it is shown that logical DIFF (ANDNOT) operations between layers can be performed fully hierarchically.>

An improved timing model for CMOS combinational logic is presented. The model is based on an analytical solution for the CMOS inverter output response to an input ramp. This model yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform. Essentially, the propagation delay is shown to be the sum of the step-response delay and an input dependent delay that may account for as much as 50-100 percent of the total delay. The matching between the ramp input and the characteristic input waveforms is shown to be easily performed for excellent agreement in output response and propagation delay. Even though the short-circuit current is neglected, its influence is shown to be small and may be corrected. As an example, the timing model is used to optimize CMOS output buffers for minimum delay. If the intrinsic output load capacitance is included in the model, the optimum tapering factor is shown to be not e but a value in the range 3-5 depending on process parameters and design style. Also, due to the input dependence of the propagation delay, the last inverter stage in the buffer should have a larger tapering factor than the other stages for minimum delay.