Recent advances in brain imaging techniques require the development of advanced models of brain networks and graphs. Previous work on percolation on lattices and random graphs demonstrated emergent dynamical regimes, including zero- and non-zero fixed points, and limit cycle oscillations. Here we introduce graph processes using lattices with excitatory and inhibitory nodes, and study conditions leading to spatio-temporal oscillations. Rigorous mathematical analysis provides insights on the possible dynamics and, of particular concern to this work, conditions producing cycles with very long periods. A systematic parameter study demonstrates the presence of phase transitions between various regimes, including oscillations with emergent metastable patterns. We studied the impact of external stimuli on the dynamic patterns, which can be used for encoding and recall in robust associative memories.

Spiking neural networks are motivated from principles of neural systems and may possess unexplored advantages in the context of machine learning. A class of convolutional spiking neural networks is introduced, trained to detect image features with an unsupervised, competitive learning mechanism. Image features can be shared within subpopulations of neurons, or each may evolve independently to capture different features in different regions of input space. We analyze the time and memory requirements of learning with and operating such networks. The MNIST dataset is used as an experimental testbed, and comparisons are made between the performance and convergence speed of a baseline spiking neural network.

The human brain is an energy hungry organ. How that brain manages its energy consumption in maintaining its health and executing sensori-motor and cognitive functions is an important but overlooked research area in contemporary cognitive neuroscience. It is argued here that the principal method whereby the human brain manages its energy utilization is through maintaining a relatively elevated level of activity in what can be referred to as “resting state networks” (RSN). The elevated energy consumption in the human brain's varied RSNs is driven and maintained by a physiological mechanism we call the Frame-Formation Energy Cycle (FFEC). Running the FFEC cycle is metabolically expensive and therefore offers a mechanism to explain the increased energy consumption in human-brain RSNs as compared to regions not involved in such networks.

Learning in the mammalian brain is commonly modeled through changing synaptic connections in cortical networks. Dynamical brain models indicate that learning leads to the formation of limit cycle oscillations across cortical areas and that the oscillatory regimes re-emerge when the learnt input is presented to the system. In this work, learning is modeled using a graph-theoretical model, which captures salient characteristics of the learning process. We introduce a random graph that combines a torus with lattice edges and additional random edges, which have power law length distribution. On this graph, we consider bootstrap percolation with excitatory and inhibitory vertices. Theoretical and numerical studies indicate the presence of various dynamical regimes on these graphs. Here, the transitions between fixed-point and limit cycle attractors are analyzed. We link this transition to changes in cortical networks during category learning, which have been observed in animal experiments using electro-cortiograph (ECoG) arrays over sensory cortices. We discuss how learning leads to categorization and strategy formation, and how the theoretical modeling results can be used for designing learning and adaptation in computationally aware intelligent machines.

SUMMARY In the paper, an field‐programmable gate array (FPGA)‐based framework is described to efficiently accelerate unstructured finite volume computations where the same mathematical expression has to be evaluated at every point of the mesh. The irregular memory access patterns caused by the unstructured spatial discretization are eliminated by a novel mesh node reordering technique, and a special architecture is designed to fully utilize the benefits of the predictable memory access patterns. In the proposed architecture, a fixed‐size moving window of the input stream of the reordered state variables is cached into the on‐chip memory and a pipelined chain of processing elements, which gets input only from the fast on‐chip memory, is used to carry out the computations. The arithmetic unit (AU) of the processing elements is generated from the data flow graph extracted from the given mathematical expression. The data flow graph is partitioned with a novel graph partitioning algorithm to break up the AU into smaller locally controlled parts, which can be more efficiently implemented in FPGA than the globally controlled AU. The proposed architecture and algorithms are presented via a case study solving the Euler equations on an unstructured mesh. On the currently available largest FPGA, the generated architecture contains three processing elements working in a pipelined fashion to provide one order of magnitude speedup compared with a high performance microprocessor and three times speedup compared with a high performance graphics processing unit. Copyright © 2013 John Wiley & Sons, Ltd.

For integers 2 les k les r, a set of binary codewords is a k-out-of-r multiple user tracing code, if from the bitwise "or" of at most r codewords one can determine at least k of them. Single user tracing codes (k = 1) were introduced by Csuros and Ruszinko (2005) and the order of magnitude of their rate was determined to be 1/r by Alon and Asodi. Here we continue this line of investigations for the case of tracing more than one user and prove that for any fixed k, the magnitude of the rate is exactly 1/r. We show further that for some non-constant k = k(r), the rate can be better than Omega(logr/r2), which is an upper bound for the rate of the union free, or superimposed codes

In this paper we deal with codes identifying sets of vertices in random graphs, that is l-identifying codes. These codes enable us to detect sets of faulty processors in a multiprocessor system, assuming that the maximum number of faulty processors is bounded by a fixed constant l. The l-identifying codes or simply identifying codes are of special interest. For random graphs we use the model G(n,p), in which each one of the (/sub 2//sup n/) possible edges exists with probability p. We give upper and lower bounds on the minimum cardinality of an l-identifying code in a random graph, as well as threshold functions for the property of admitting such a code. We derive existence results from probabilistic constructions. A connection between identifying codes and superimposed codes is also established.

The zero-error capacity region of r-out-of-T user multiple-access OR channel is investigated. A family F of subsets of [n] = {1, ..., n} is an r-single-user-tracing superimposed code (r-SUT) if there exists such a single-user-tracing function /spl phi/:2/sup [n]/ /spl rarr/ F that for all F' /spl sube/ F with 1 /spl les/ |F'| /spl les/ r, /spl phi/(/spl cup//sub A/spl isin/F/'A) /spl isin/ F'. In this correspondence, we introduce the concept of these codes and give bounds on their rate. We also consider disjointly r-superimposed codes.

We investigate the zero-error capacity region of r-out of T user multiple access OR channel. A family /spl Fscr/ subsets of [n]={1, . . . ,n} is an r-single-user-tracing superimposed code (r-SUT) if there exists such a single-user-tracing function /spl phi/: 2/sup [n]//spl rarr//spl Fscr/ that for all /spl Fscr//spl sube//spl Fscr/ with |/spl Fscr/'|/spl les/r, /spl phi/(/spl cup//sub A/spl isin///spl Fscr//sub '/A)/spl isin//spl Fscr/'. In this paper we introduce the concept of these codes and investigate bounds on their rate. We also consider disjointly r-superimposed codes.

A family of n-dimensional unit norm vectors is an Euclidean superimposed code if the sums of any two distinct at most m-tuples of vectors are separated by a certain minimum Euclidean distance d. Ericson and Gyorfi (1988) proved that the rate of such a code is between (log m)/4m and (log m)/m for m large enough. In this paper-improving the above long-standing best upper bound for the rate-it is shown that the rate is always at most (log m)/2m, i.e., the size of a possible superimposed code is at most the root of the size given by Ericson et al. We also generalize these codes to other normed vector spaces.

Pippenger (1981) showed in a probabilistic way that the capacity of a collision channel with multiplicity feedback is one. In this correspondence, using an Erdos-Renyi type search strategy, we settle a long-standing open problem by giving a constructive proof of this result. Moreover, we prove that two different capacity definitions are equivalent, thereby solving a problem posed by Tsybakov (1985).