A fully-integrated half-bridge driver with dual N-type power transistors is proposed in this paper, which adopts on-chip charge pumps with integrated capacitors based on charge sharing to avoid external bootstrap components. Without bootstrap-capacitor charging paths through low-side power transistors and high-frequency high-power switching nodes, overcharge and large electro-magnetic interference (EMI) can be avoided by eliminating parasitic interconnect inductance and body diode. Adaptive dead time is employed to enhance efficiency, enabling the system to achieve appropriate dead times in various applications. Besides, 100% duty-cycle control is realized by duty-cycle detection and additional continuous charge pump, which can charge the on-chip driver capacitor during on-time, the restriction of minimum off-time is eliminated and the proposed driver can work at full duty cycle range. The proposed charge-sharing-based (CSB) half-bridge driver with any duty-cycle capability embedded in a buck converter with 2A load is implemented in a 0.18 μm BCD technology, which occupies an active area of 0.151mm2. Verification results demonstrate that a 2.2 MHz switching frequency is realized with 2.4V–5.5V input voltage and a peak efficiency of 96.8% is achieved for 5 to 4V conversion. The minimum regulation voltage difference between input voltage and output voltage is 70 mV with the help of 100% duty-cycle circuit.

In HV (high-voltage) and HF (high-frequency) applications, SiC (silicon carbide) MOSFET is widely used for its small parasitic characteristics and fast switching speed. Using discrete devices on PCB, the active gate driver is usually adopted to restrict EMI (electromagnetic interference) noise. This method could achieve a limited switching performance improvement, and many disadvantages still exist. In this paper, the integrated adaptive multi-level gate driver is presented to improve the switching performance of SiC MOSFET in HV and HF applications. The proposed gate driver is realized on the chip using critical techniques such as dV/dt noise attenuation, high-speed circuit, and anti-false triggering mechanism. Then, the proposed gate drive is fabricated in a$0.18~\mu \text{m}$BCD process and occupies a 4.16 mm2 active area. The experimental results show that SiC MOSFET can achieve a 200 ns switching time, 0.8 mJ energy losses, no more than 15 V/ns average dV/dt noises, and 1.5 A/ns average di/dt noises under a 600 V power supply and a 33 A load. SiC MOSFET can also realize the excellent switching performance at different load currents from 15 A to 90 A by using the proposed adaptive multi-level gate driver.

The primary-side regulation (PSR) flyback converters with the feature of constant current (CC) and constant voltage (CV) are widely used in charger systems and adaptors of electronic devices. However, the conventional method of CC control is complex and inaccuracy, and more circuits should be added to improve accuracy causing more complex design and larger cost. In this paper, a novel strategy of CC control strategy based on large signal control is proposed to achieve simple and high-precision CC control which operates seamlessly as working state switched between CC and CV. The control chip is implemented in a 0.18μm BCD process, and the deviation of output current in CC mode is less than ± 2% without loop compensation. It well meets the demand of large charging current in startup and limiting current under low voltage condition.

In high switching frequency applications, for the purpose of the high efficiency and low electromagnetic interference (EMI), an adaptive soft switching technique is proposed in this paper. According to the resonance characteristics of system, a valley point detection circuit is designed. Besides, considering the driving delay of power MOSFET, an adaptive control circuit is proposed to generate a flag signal of driver, by which the adaptive zero voltage switching (AZVS) can be achieved. With the help of proposed AZVS, the precise zero voltage switching independent of driving delay and type of power MOSFET can be automatically realized. An AZVS control circuit is implemented in a 0.35μm BCD process. It allows high efficiency and low EMI, as well as good thermal performance.

In this paper, a MOSFET-only voltage reference with novel curvature-compensation is proposed. In order to reduce the temperature coefficient in the proposed voltage reference, two proportional to absolute temperature voltages with opposite second-order order TC are added on a threshold voltage, which is achieved by a resistorless threshold voltage extractor. Besides, self-biased current source with feedback is realized at the same time, which can provide bias current for the whole voltage reference and enhance the performance of generated voltage reference without additional power consumption. Verification results of the proposed voltage reference implemented with 0.35µm technology process show that the temperature coefficient is 2.4 ppm/□ with a temperature range of −20□ to 80□ is obtained, and a 62.9 dB power supply rejection ratio is achieved with a 68nA maximum supply current.