This paper describes the design of a neural network that performs the phonetic-to-acoustic mapping in a speech synthesis system.The use of a time-domain neural network architecture limits discontinuities that occur at phone boundaries.Recurrent data input also helps smooth the output parameter tracks.Independent testing has demonstrated that the voice quality produced by this system compares favorably with speech from existing commercial text-to-speech systems.

The bit rate for the speech and channel coder for the half-rate GSM channel is 11400 bps. A 5600 bps VSELF speech coder designed for this application is described. This speech coder is one of two candidates being considered by GSM channel for the half-rate channel. It employs a novel strategy for vector quantization of the reflection coefficients (rj), which combines high coding efficiency, low codebook search complexity, and low storage requirements. A computationally streamlined version of a zero-pole spectral noise weighting function is implemented. An adaptive pitch prefilter and an adaptive spectral postfilter are used to improve the speech coder's performance for both the tandemed and non tandemed cases.

Techniques for improving the performance of CELP (code excited linear prediction)-type speech coders while maintaining reasonable computational complexity are explored. A harmonic noise weighting function, which enhances the perceptual quality of the processed speech, is introduced. The combination of harmonic noise weighting and subsample pitch lag resolution significantly improves the coder performance for voiced speech. Strategies for reducing the speech coder's data rate, while maintaining speech quality, are presented. These include a method for efficient encoding of the long-term predictor lags, utilization of multiple gain vector quantizers, and a multimode definition of the speech coder frame. A 5.9-kb/s VSELP speech coder that incorporates these features is described. Complexity reduction techniques which allow the coder to be implemented using a single fixed-point DSP (digital signal processor) are discussed.>

Techniques for improving the performance of CELP (code excited linear prediction) type speech coders while maintaining reasonable computational complexity are explored. A harmonic noise weighting function which enhances the perceptual quality of the processed speech is introduced. The combination of harmonic noise weighting and subsample resolution pitch significantly improves the coder performance for voiced speech. A 6.9 kb/s VSELP speech coder which incorporates subsample resolution pitch and harmonic noise weighting is described. Complexity reduction techniques are discussed which allow the coder to be implemented using a single fixed point digital signal processor.>

The vector sum excited linear prediction speech coder is presented. It utilizes a codebook with a structure that allows for a very efficient search procedure. Other advantages of the VSELP codebook structure are discussed, and a detailed description of an 8-kb/s VSELP coder is given. This coder was selected by the Telecommunications Industry Association (TIA) as the standard for use in North American digital cellular telephone systems. The coder uses two VSELP excitation codebooks, a gain quantizer which is robust to channel errors, and a novel adaptive pre/postfilter arrangement.>

The architecture and features of the Motorola DSP56200 are described. The DSP56200 is an algorithm-specific cascadable digital signal processing peripheral designed to perform the computationally intensive tasks associated with finite impulse response (FIR) and adaptive FIR digital filtering applications. The DSP56200 is implemented in high-performance, low-power 1.5- mu m HCMOS technology and is available in a 28-pin DIP package. The on-chip computation unit includes a 97.5-ns 24-bit*24-bit coefficient RAM, and a 256-bit*16-bit data RAM. Three modes of operation allow the part to be used as a single, dual, or single adaptive FIR filter, with up to 256 taps per chip. In the adaptive mode, the part performs the FIR filtering and least-mean-square (LMS) coefficient update operations for a single tap in 195 ns, permitting use of the part as a 19-kHz sampling rate, 256-tap adaptive FIR filter. A programmable DC tap, coefficient leakage, and adaptation coefficient parameters in the adaptive FIR mode allow the DSP56200 to be used in a wide variety of adaptive FIR filtering applications. The performance of the part in an echo canceler configuration is presented. Typical applications of the part are also described.>

This paper describes the architecture and features of the Motorola DSP56200, an algorithm-specific cascadable digital signal processing peripheral designed to perform the computationally intensive tasks associated with FIR and adaptive FIR digital filtering applications. The DSP56200 is implemented in high performance, low power 1.5µm HCMOS technology and is available in a 28 pin DIP package. The on-chip computation unit includes a 97.5 ns 24×16-bit multiplier with a 40-bit accumulator, a 256×24-bit coefficient RAM, and a 256×16-bit data RAM. Three modes of operation allow the part to be used as a single FIR filter, a dual FIR filter, or a single adaptive FIR filter, with up to 256 taps/chip. In the adaptive FIR filter mode, the part performs the FIR filtering and LMS coefficient update operations for a single tap in 195 ns, permitting use of the part as a 19 kHz sampling rate, 256 tap adaptive FIR filter. Programmable DC tap, coefficient leakage, and adaptation coefficient parameters in the adaptive FIR mode allow the DSP56200 to be used in a wide variety of adaptive FIR filtering applications. The performance of the part in an echo canceller configuration will be presented. Typical applications of the part will also be described.

A High Performance Processor design is described which is employed in the study of digital signal processing techniques. The processor is seen to enhance algorithm development as a high speed peripheral to a general purpose minicomputer facility. In addition, it can operate in a stand-alone mode and has been used to implement a real-time Linear Predictive vocoder system.