The power consumed when writing to some emerging memory arrays, such as certain varieties of Resistive Random Access Memory (RRAM), is significantly greater than that consumed by many charge-based memories such as SRAM. As a result, when used in applications where instantaneous power consumption is constrained, the number of bit transitions is limited. In this paper, we present modular, low cost, power-efficient differential bus encoders (DBEs) and (related) encoders for error correcting codes. Combining a DBE module and an encoder for a power-efficient single error correcting (PESEC) code ensures low-power operation and reliable data storage, and with a minor modification, a PESEC encoder becomes a PESEC+DED encoder. These encoders make use of systematic, multiple-representation based, error correcting codes. It is shown that when one of our DBEs is used with one of these PESEC encoders, the combined system requires about twenty-five percent fewer bit transitions and ten to twenty percent fewer redundant bits than similar techniques. Moreover, the addition of a PESEC encoder only causes a marginal change in implementation cost relative to that of an encoder for a standard Hamming code. Furthermore, the techniques proposed here do not require huge lookup tables, as do other power-aware techniques. Finally, our PESEC encoders can be used withanybus encoder.

Certain emerging memory technologies such as Resistive RAM (RRAM) require a relatively large amount of energy when changing the value of a bit. When working under strict instantaneous power constraints, it is necessary to limit the maximum number of bit transitions (bit-flips) that can be made when writing a word. To this end, binary, power-efficient, double-error-correcting (PEDEC) codes are introduced. For standard data widths (multiples of eight bits), PEDEC codes offer reductions in both the number of bit transitions and the memory width. PEDEC codes are encoded systematically, and their redundant part is generated by making use of coset codes that are carefully designed so that their coset leaders are easy to generate. For this reason, PEDEC codes do not require the very large lookup tables required by the competing codes and can be concatenated with any bus encoder.

The power consumed when writing to Resistive Random Access Memory (RRAM) is significantly greater than that consumed by many charge-based memories such as SRAM, DRAM and NAND-Flash memories. As a result, when used in applications where instantaneous power consumption is constrained, the number of bits that can be set or reset must not exceed a certain threshold. In this paper, we present a power-efficient, single error correcting (PESEC) code for memory macros, which, when combined with bus encoding, ensures low-power operation and reliable data storage. This systematic, multiple-representation based single-error correcting code provides a relatively high rate, with a marginal increase in implementation cost relative to that of a standard Hamming code, and it can be used with any bus encoder.

Bus encoding is a technique for decreasing the power consumption of a chip by reducing the number of bit transitions during data transmission over a bus or during memory write operations. Designers often concatenate a bus encoder with an error correcting code (ECC) encoder to guarantee the reliable and power-aware transmission of data. This paper introduces a structured technique for hardening bus-encoders to enable single error correction (SEC) while maintaining power awareness. The method is based on expurgating the Hamming code in a specific manner. The resulting power-aware (expurgated), SEC code can serve as an add-on solution, when it is desired to add error correction to an existing bus-encoder.

Side-channel attacks represent a significant and persistent threat to hardware security. One effective strategy for safeguarding hardware components against these attacks involves the implementation of masking schemes. Among these schemes, Inner Product Masking (IPM) has received considerable attention and analysis in prior research. Inner Product Masking with Error Detection aims to extend the security provided by IPM to Fault-Injection attacks. This can be achieved by incorporating (linear) repetition code for fault detection (IPM-FD) or by integrating a non-linear robust error detection into the scheme (IPM-RED). IPM-RED can detect (with non-zero probability) every fault regardless the number of bits it flips. However, this robustness comes with a cost, a non-linear function may leak via the physical channels more information than a linear one. This paper shows that information leakage from IPM-RED is marginal. An improved IPM-RED masking scheme is also presented, and an empirical side-channel leakage analysis of the protected Advanced Encryption Standard (AES) design utilizing the Test Vector Leakage Assessment (TVLA).

Often, data stored in memory must be protected from naturally occurring and malicious errors. Methods for constructing codes that are robust with respect to errors injected into the data as well as into the address (in which the data are to be stored) are described. Several ways of extending data-protecting codes to address-and-data protecting codes are presented, and a generalization of the concepts behind CPCs – low cost codes for which no error injected into the data is ever completely masked – is given. A fundamental difference between attacks on the address and data and attacks that only target the data is detailed, and the consequences of this fundamental difference are briefly considered.

A hardware-based control flow monitoring technique enables the detection of errors in both the control flow and the instruction stream executed on a processor. However, as shown in recent publications, these techniques fail to detect malicious carefully-tuned manipulations of the instruction stream in a basic block. This article presents a non-linear encoder and checker that can cope with this weakness. It is a MAC based control flow checker that has the advantage of working with basic blocks of variable length, can detect every error, and performs the computation in real-time. The architecture can easily be modified to support different signature size and error masking probabilities.

It has been previously shown that hardware implementation of fault attack countermeasures based on error-detecting codes (EDCs) can make the circuit more vulnerable to power analysis attacks. We revisit this finding and show that the hypothesis space can grow significantly when a state-of-the-art security-oriented robust EDC is properly crafted. We use the Roth-Karp decomposition as an analytical tool to prove that by a simple re-ordering of the EDC's bits, the number of extra bits needed to formulate the hypotheses becomes so large that power analysis (that tries to exploit additional information from the redundant bits) is rendered infeasible.

Compact protection codes (CPCs) provide optimal protection against fault injections attacks on memory arrays content. Nevertheless, CPCs fail to detect errors injected into the address itself. Consequently, an adversary can write a correct data word to an erroneous address without being detected. This paper presents an efficient code, dubbed AD-CPC, which detects both data manipulations and faults injected into the address decoder. No additional redundancy bits are required and no latency is introduced. In addition, the new encoding has a negligible effect on the error masking probability of the original CPC. We provide theoretical bounds and experimental results that support these claims. We show that with r additional redundant bits every error can be detected with probability of at least 1 - 3.2-r.

A hardware-based control flow monitoring technique enables to detect both errors in the control flow and the instruction stream being executed on a processor. However, as was shown in recent papers, these techniques fail to detect malicious carefully-tuned manipulation of the instruction stream in a basic block. This paper presents a non-linear encoder and checker that can cope with this weakness.

Side channel analysis attacks are considered an extreme hardware security hazard for cryptographic devices. There are numerous approaches to prevent attackers from extracting useful information from secured devices. Nonetheless the cost of implementing an effective countermeasure is usually very high in terms of area/performance. In this paper we propose a novel approach to the temporal redistribution of the power information. Specifically, we present a circuit level methodology that makes it possible to manipulate the three main parameters of the current profile during the clock period: the start time of the computation, the duration and the amplitude. The effectiveness of the proposed countermeasure was evaluated on a 4-bit cryptographic function in a 65nm TSMC process. The simulation results indicate that the number of secret bits that leaked from the protected design (i.e., the mutual information) was reduced dramatically from 4 bits to 0.85 bits. In addition, at least 1500 ideal noise-free power traces were required to extract these bits, whereas less than 150 traces were required to extract the whole 4 bits from the unprotected design. The sensitivity of the protected circuit to process and environmental variations are minimal, with measured standard deviation of 0.1bit. The area overhead is up to 32%.

Transmission across a bus modelled as a parallel asynchronous communication channel is subject to fault injection attacks which cause glitches - pulses that are added to the transmitted signal at arbitrary times - and delays. We present self-synchronizing coding schemes with no latency at the receiver that do not require any acknowledgment to be sent and that can decode the received signal even when the signal suffers from random delays and distortion by random glitches. We make use of the codes to produce lower bounds on the information capacity of such channels when the number of parallel channels is large.

Robust codes C(n, k)qare nonlinear q-ary codes of dimension k and length n ≤ 2k. Robust codes can detect any error with nonzero probability; hence, they can effectively detect fault injection attacks. Most high rate robust codes are either restricted to certain ratios between n and k, or have relatively high hardware complexity. This paper presents new constructions for optimum or close to optimum low complexity high rate robust codes. These codes exist for any k and n. The hardware complexity of each construction is discussed, and a method to choose the one with the smallest implementation cost is presented.

Information leakage through physical channels is a major hurdle in embedded hardware security. This paper overviews the three key factors in the embedded hardware security space, focusing on gray-box (bounded resources) power analysis attacks: the adversary's knowledge and abilities, the security metrics used by adversaries' and security evaluators and gate-level countermeasures. A new design paradigm, dubbed pAsynch, that utilizes internal signals and random signals to uniformly spread the information-carrying energy within the clock period in a specific way with a resolution below the band-width and noise-filtering abilities of advanced measurement equipment is introduced. The advantages and design challenges introduced by the pAsynch paradigm are discussed.

Leakage of information through the power supply current has become a major factor in logic design. In this paper, a low cost and simple to employ design methodology dubbed pseudoasynchronous is presented. This design style combines the security advantages of asynchronous circuits with the ease of synchronous circuit design. Randomization and data-dependencies (DD) are utilized to hide information leakage from the current dissipation, and hence making the critical synchronization of power supply current traces hard to do. In addition, randomization and DD are utilized for both time-domain hiding of information leakage during the active region (dynamic currents) and for amplitude-domain hiding of information leakage during the static-region (leakage currents). The main advantages of this new approach are low area cost, reduced signal, and increased noise. Circuit-level analyses show that it is harder to exploit the information leakage from internal signals of the proposed design than from CMOS-based synchronous designs or other forms of time-domain hiding countermeasures.

Codes that aim to detect any error regardless of its multiplicity are referred to as security oriented codes. Most of these codes are designed to protect uniformly distributed codewords; there are few solutions which are used in protecting systems with non-uniformly distributed words. The paper introduces a new encoding method, termed “Level-Out encoding”, for cases in which some words are more likely to appear than others and compares the effectiveness of the different methods. The advantage of the suggested coding scheme is demonstrated by simulations with two different types of attackers - a Blind Attacker, limited to the knowledge of the a priori information word and codeword distribution, and a Memory Based Attacker with access to the conditional probabilities based on previous information words as well.

Transmissions across asynchronous communication channels are subject to delay injection attacks, which can cause an arbitrary number of skews. That is, such attacks can cause an arbitrary number of transmitted signals to arrive after the first signal of the next transmission has arrived. The (common) assumption that despite the delays, all signals from the ith transmission arrive at the decoder before any signal from the (i+2)nd transmission arrives is called a no switch assumption. This paper presents a self-synchronizing, zero-latency, zero-error coding scheme that requires no acknowledge and can decode transmissions distorted by an arbitrary number of skews that obey this no switch assumption. The rate associated with the coding scheme provides a lower bound of 0.6942 for the (zero-error) capacity of such a channel. It is further shown that zero-error channel capacity of the channel is upper bounded by 0.7248. Finally, this paper presents bounds on the (zero-error) capacity of a channel for which the number of transmissions that can mix with one another is large.

First-order and high-order correlation-power-analysis attacks have been shown to be a severe threat to cryptographic devices. As such, they serve as a security measure for evaluation and comparison of security-oriented implementations. When properly designed, data-dependent delays can be used as a barrier to these attacks. This paper introduces a security-oriented delay assignment algorithm for mitigating single and multibit attacks. The algorithm enables a reduction of the correlation between the processed data and the consumed current by utilizing the data-dependent delays as a source of correlated noise. This is done while minimizing the area overhead, propagation time, and power. We show that for the same security level this new algorithm provides X2 and X6 more area efficiency, and X1.5 and X2.25 higher frequencies than a permuted path delay assignment and random embedding of delay elements.

Transmission across asynchronous communication channels can be subjected to delay injection attacks. Delay injection attacks cause arbitrary skews - arbitrary numbers of transmitted signals can arrive after the first signal of the next transmission has arrived. The (common) assumption that all signals form the ithtransmission arrive at the decoder before any signal from the (i + 2)thtransmission arrives is called a no switch assumption. This paper presents a self-synchronizing zero-latency coding scheme that requires no acknowledge and can perfectly decode any transmission distorted by an arbitrary skew that obeys the no switch assumption.

Security-oriented error-detecting codes are used to detect fault injection attacks on cryptographic devices. These codes are usually designed for uniformly distributed codewords, i.e., for codes that have maximal entropy. In practice, the codewords are not uniformly distributed; thus, their entropy is smaller and their efficiency in detecting attacks degrades. This paper analyzes the relation between the entropy of a code and its worst error masking probability. Based on this relation, a method for determining the rate and structure of a code that provides the required error masking probability is presented.

Side channel attacks have become one of the most significant problems in modern digital systems. In particular, differential power analysis (DPA) has emerged as a powerful technique because it does not require any assumptions regarding the hardware implementation of a crypto-chip. In this paper, a new randomized multitopology logic (RMTL) is proposed to enhance immunity to DPA. RMTL refers to a family of dedicated security-oriented gates whose power profile cannot be predicted by external observers. Specifically, each gate of this logic can be configured in real time to operate in a different circuit topology, where each topology induces a different power profile. Immunity to DPA attacks is obtained by randomly changing each gate's topology on run time. The suggested approach can coexist with common existing countermeasures. Theoretical analysis and simulation results, conducted in a standard 40-nm technology, clearly show higher immunity to DPA attacks when using the proposed approach compared with standard CMOS implementation.

Security oriented codes are considered as one of the most efficient countermeasures against fault injection attacks. Their efficiency is usually measured in terms of their error masking probability. This criterion is applicable in cases where it is possible to distinguish between random errors and malicious attacks. In practice, if the induced errors are not fixed for several clock cycles, it is difficult to distinguish between the two. Moreover, a decoder that tries to correct the tampered word can conceal the fact that the device is under attack. This paper defines a new criterion, named t-robustness, for evaluating the efficiency of robust codes that provide both reliability and security. An error correcting code is called t-robust, if it can correct up to t errors and at the same time detect any attack that changes the data. The paper presents a general structure for concatenated codes that have this property.

Security-oriented codes are used in cryptographic devices to maximize the probability of detecting fault injection attacks. This paper introduces a new class of binary security-oriented codes of rate >1/2. The codes are derived from the cubic code by applying a linear transformation on the codewords before puncturing. The codes are systematic and robust in that any nonzero error can be detected with a probability >0. The error masking probability of the codes is upper bounded by 2-r+1where r is the number of redundancy bits. It is shown that in some cases, by choosing the proper transformation and puncturing matrices, it is possible to increase the minimum distance of the code, or to reduce the maximal error masking probability to meet its lower bound.

The paper presents an embedded self test circuit for adaptive systems whose exact specification is unknown. In particular, a functional testing mechanism for systems that have an acceptable representation as polynomials of low order is introduced. The testing mechanism is based on linear-checks and is suitable for Walsh transform based architectures. The paper shows that it is possible to define a small set of linear-checks which does not depend on the actual functionality that the hardware has converged to. Moreover, the check-set can be defined even without knowing the number of input variables nor their precision. In addition, the implementation cost of this testing scheme is negligible in respect to the cost of overall system.

Robust and partially robust codes are codes used in cryptographic devices for maximizing the probability of detecting errors injected by malicious attackers. The set of errors that are masked (undetected) by all codewords form the detection-kernel of the code. Codes whose kernel contains only the zero vector, i.e. codes that can detect any nonzero error (of any multiplicity) with probability greater than zero, are called robust. Codes whose kernel is of size greater than one are considered as partially-robust codes. Partially-robust codes of rate greater than one-half can be derived from the the cubic Karpovsky-Taubin code [6]. This paper introduces a construction of robust codes of rate >; 1/2. The codes are derived from the Karpovsky-Taubin code by puncturing the redundancy bits. It is shown that if the number of remaining redundancy bits (r) is greater than one then the code is robust and any error vector is detected with probability 1, 1-2-ror 1 - 2-r+1. The number of the error vectors associated with each probability is given for robust codes having odd number of information bits.

The paper studies a new polynomial representation of Multi Output Functions (MOFs). The new representation, called GITE-polynomials, is based on a newly introduced Generalized If-Then-Else (GITE) function. Being a compact form of representation of MOFs, the GITE-polynomials allow efficient manipulation with a set of functions. The paper introduces algebra of GITE-polynomials. Properties of this algebra are used for solving the MOF-decomposition problem. The solution provides a compact representation of MOFs.

A Trojan horse is a malicious altering of hardware specification or implementation in such a way that its functionality is altered under a set of conditions defined by the attacker. The paper presents a technique for designing secure systems that can detect an active Trojan. The technique is based on utilizing specific information about the system's behavior, which is known to the designer of the system and/or is hidden in the functional specification of the system. A case study of the proposed technique conducted on an arithmetic unit of a microprocessor is provided. The study indicated a high level of Trojan detection with a small hardware overhead.

This paper deals with the number of paths in multiterminal binary decision diagrams (MTBDDs) and shared binary decision diagrams (SBDDs) representing a set of Boolean functions. It is shown that the number of paths in an MTBDD (SBDD) can be uniquely determined by values of specific weighted-autocorrelation coefficients. An analytical expression for the number of paths as a linear function of the values of the weighted-autocorrelation coefficients is presented. Based on this expression, a method of minimization of the number of paths is proposed. The method is based on replacing the initial set of input variables with their linear combinations. By using this method, a deterministic paths-reduction procedure, which provides MTBDDs and SBDDs with a reduced number of paths, is presented. The efficiency of the suggested approach is demonstrated on benchmark functions.

This paper presents generalizations of the Karpovsky-Taubin nonlinear code. The generalizations lead to robust and partially robust single error detecting codes and single error correcting codes.

The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault tolerant nano-PLAs, the area and the number of crosspoint devices, are considered as optimization criteria for the synthesis. The paper introduces a method for synthesizing fault tolerant nano-PLA based FSMs. The method is based on decomposing an initial PLA description of the FSM into a three interacting portions. The proposed solution provides significant reduction of the area without meaningful increasing of a number of crosspoint devices in comparison with known solutions and provides a trade-off between the area and the number of devices in designing FSMs by PLAs.

This paper deals with analytic methods for the calculation and reduction of the average path lengths (APLs) in binary decision diagrams (BDDs). Usually, information-theoretic measures and information-theoretic techniques are used to construct BDDs of minimal APLs. Specifically, the mutual information between a Boolean function and its variables and the Shannon-Fano prefix coding are utilized. This paper deals with the problem of the APL reduction by using spectral techniques. Particularly, methods based on the properties of the Walsh spectrum of a Boolean function and its autocorrelation function are discussed. It is shown that the APL is a linear function of the autocorrelation values, that is, the APL depends on the Boolean function's properties in the time domain (autocorrelation) rather on the Boolean function's properties in the frequency domain (Walsh spectrum). In addition, it is shown that information-theoretic criteria like the mutual information or the conditional entropy are equivalent to frequency-domain criteria. Consequently, existing information-theoretic approaches for APL reduction that are based on mutual-information criterion or the Walsh transform coefficients may derive a suboptimal APL. The representation of the APL as a function of the autocorrelation values opens a way to determine the optimal ordering of the input variables analytically. Two procedures for APL reduction by ordering and by using linear combinations of the input variables are presented: (1) minimization by using the autocorrelation values and (2) minimization by using the mutual information between the Boolean function and a linear function of the input variables. The time-domain approach may derive a linearized BDD of a lower APL, whereas the information-theoretic approach has a lower computational complexity with comparable performance. Experimental results show the efficiency of the suggested techniques.

This paper discusses reduction of the number of product terms in representation of totally symmetric Boolean functions by Sum of Products (SOP) and Fixed Polarity Reed- Muller (FPRM) expansions. The suggested method reduces the number of product terms, correspondingly, the implementation cost of symmetric functions based on these expressions by exploiting Gray decoding of input variables. Although this decoding is a particular example of all possible linear transformation of Boolean variables, it is efficient in the case of symmetric functions since it provides a significant simplification of SOPs and FPRMs. Mathematical analysis as well as experimental results demonstrate the efficiency of the proposed method.

The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades followed by parity checking their output logic. The algorithm for partitioning the scheme into cascades is provided. An universal scheme of finite state machine (FSM) with the cascade errors detection is presented and investigated. The scheme does not require any redundant coding variables. Benchmark results are presented and show significantly low overhead requirement

We derive a new estimate for the error term in the binomial approximation to the distance distribution of BCH codes. This is an improvement on the earlier bounds by Kasami-Fujiwara-Lin (1985), Vladuts-Skorobogatov (1991), and Krasikov-Litsyn (1995).

We introduce a family of binary array codes of size t/spl times/n, correcting multiple phased burst erasures of size t. The codes achieve maximal correcting capability, i.e., being considered as codes over GF(2/sup t/) they are MDS. The length of the codes is n=/spl Sigma//sub l=1//sup L/(/sub l//sup t/) where L is a constant or is slowly growing in t. The complexity of encoding and decoding is proportional to rnmL where r is the number of correctable erasures, and m is the smallest number such that 2/sup t/=1 modulo m. This compares favorably with the complexity of decoding codes obtained from the shortened Reed-Solomon codes having the same parameters.

A family of binary array codes of size (p-1)/spl times/n, with p a prime, correcting multiple column erasures is proposed. The codes coincide with a subclass of shortened Reed-Solomon codes and achieve the maximum possible correcting capability. Complexity of encoding and decoding is proportional to rnp, where r is the number of correctable erasures, i.e., is simpler than the Forney decoding algorithm. The length n of the codes is at most 2p-1, that is, twice as big as the length of the Blaum-Roth codes having comparable decoding complexity.