This paper presents a PVT-resilient, subthreshold SRAM-based computing-in-memory (CIM) macro tailored for energy-efficient spiking neural networks (SNNs). The macro integrates in-situ current sensors and distributed voltage regulators to enable robust large-scale (1024 wordlines, 1304 bitlines and 128 shared neuron cells) subthreshold current-mode CIM, mitigating energy overheads and process-voltage-temperature (PVT) sensitivity. The neuron cells adopt a programmable, memory cell-based firing threshold to enhance neuron robustness against PVT variations. The architecture uses a stride-tick batching schedule to significantly reduce buffer overhead with enhanced input data reuse. Exploiting the high sparsity of SNNs, the proposed system demonstrates significant improvements in energy efficiency and variation tolerance. Fabricated in 28-nm CMOS, the prototype attains 93.64\% accuracy on keyword spotting, delivers up to 1181.42 TOPS/W, and achieves 7.24 TOPS/mm^2, demonstrating a viable and efficient solution for high-performance edge SNN processing.

This article presents the design of simultaneous bidirectional (SBD) transceivers (TRX) for system chips interconnects. Implemented on differential channels, the forward link employs common-mode non-return to zero (NRZ) signaling, while the backward link utilizes differential-mode 4-level pulse amplitude modulation (PAM-4) signaling. The SBD transceiver architecture integrates an NRZ transmitter and two PAM-4 receivers in the Host Chip, paired with an NRZ receiver and two PAM-4 transmitters in the Client Chip. This configuration enables source-synchronous, multi-rate operation without the need for explicit clock channels. The SBD link supports forward data rates ranging from 6 to 12.8 Gbps and backward data rates from 12 to 25.6 Gbps. To the authors’ best knowledge, the proposed SBD link achieves the broadest tunable data rate as is reported to date. An experimental prototype is implemented using a TSMC 28nm CMOS process. The die areas for the Host Chip and the Client Chip are approximately 0.46 mm2and 0.28 mm2respectively. The SBD transceiver demonstrates an energy efficiency of approximately 2.5 pJ/b.

A time-domain stochastic flash ADC was fabricated using a 12-nm FinFET technology. Its analog input in the voltage domain is transformed into time-domain pulses, which are then sent to a time-to-digital converter (TDC) comprising 405 time comparators. To distinguish the signal timing amplitude, the random input-referred offsets of these comparators are utilized. An input distribution network is employed to broaden the input range of the TDC. A code-mapping calibration method is used to improve the conversion linearity and mitigate the effects of variations in process, voltage, and temperature. Operating at a 12-GS/s sampling rate, the ADC chip consumes 110.7 mW from a 0.8 V supply. It occupies an active area of$480\times 125~\mu \text {m}^{2}$. The ADC achieves an SNDR better than 40.5 dB and an SFDR better than 50.7 dB for input frequencies up to 5.8 GHz.

Due to popular requests from the designers of clock and data recovery (CDR) regarding the inefficiency of generating high accuracy phase interpolator (PI), in this work, we have developed a layout generator for such circuit, different from conventional constraint-driven works. In the first stage, we propose a customized template floorplanning plus pin generation demanded by the users. In the second stage, in order to generate high accuracy layout, we implement a gridless router for signal, power supply and clock. Experiments with several configurations indicate that our approach can generate high-quality corresponding layouts that align with user expectations, and even surpass the quality of manual designs on structurally regular high-performance PIs, which are not easy and efficient to be generated by prior primitive/grid-based methods.

ADC-DSP-based PAM-4 receivers are widely used in 100+ Gbps data links to compensate for high channel losses through flexible digital equalization. To support applications ranging from very short- to long-reach, where channel loss can vary by over 20 dB, it is crucial to incorporate both channel-adaptive ADCs and equalizers for optimizing energy efficiency during operation. This paper introduces a system controller with an integrated SNR monitor that dynamically reconfigures the ADC resolution and FFE tap count in the background. By maintaining a relatively constant SNR at the input of the PAM-4 demodulator, hardware resources are co-optimized to reduce power consumption while achieving a target bit error rate (BER) of 10-6. A digital engine for a 112 Gb/s PAM-4 receiver, featuring a 1-tap DFE and reconfigurable ADC and FFE, is implemented to handle channel losses ranging from 12.4 dB to 34.5 dB. By automatically reducing the ADC resolution and FFE taps from 6 to 5 bits and from 24 to 6 taps, respectively, power savings of over 40% are achieved.

This paper describes the design of a 32 Gb/s four-level pulse amplitude modulation (PAM-4) optical transceiver in a 40 nm CMOS technology. At the transmitter side, the laser driver is composed of an asymmetric waveform equalizer, a 3-tap feed-forward equalizer (FFE), and a novel active-back termination (ABT) circuit. The ABT circuit provides a self-tracking, tunable source impedance to match the characteristic impedance of different laser diodes. At the receiver side, the fully integrated optical receiver consists of a transimpedance amplifier, a variable gain amplifier, an automatic threshold tracking circuit (ATC), and a quarter-rate decision feedback equalizer (DFE). By using the adaptive ATC, it reduces the BER induced by the harmonic distortion along the signal path by more than 27X. Both the ATC and DFE are automatically adapted by an on-chip sign-sign LMS (SSLMS) engine. Fabricated in TSMC 40 nm CMOS process, the chip area for the transmitter and receiver are about 0.029 mm2and 0.23 mm2. The power consumptions are about 146.8 mW and 128.8 mW respectively for the PAM-4 transmitter and receiver.

Modern analog placement techniques require consideration of current path and symmetry constraints. The symmetry pairs can be efficiently packed using the symmetry island configurations, but not all these configurations result in minimum gate interconnection, which can impact the overall circuit routing and performance. This article proposes the first work that reformulates this problem considering all of them together in the form of parallel current path (PCP) constraints. PCP constraints, in addition to monotonic current paths, also consider partial-monotonic current paths to generate a more compact placement. We use a novel two-step approach to detect symmetry-feasible sequence-pairs (SFSPs) without doing placement construction by using representative sequence-pair (RSP). Then a placement algorithm satisfying these constraints is formulated to reduce a vast search space via efficient sequence pair manipulation. The experimental results show that this formulation and algorithm can generate multiple placement solutions that satisfy all the constraints in a more tightly packed configuration, resulting in smaller wirelength, reduced parasitics, and thus better post-layout performance.

A single chip optical receiver comprising of a fontend amplifier, a CDR, and a 1:4 demultiplexer is presented. Incorporating with an integrating type receiver front-end, a baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operation. Besides, a hybrid loop filter consisting of analog decimation and digital post processing is proposed for high speed operation with low power consumption. By applying a PRBS 231-1 test pattern, the input sensitivity of the optical receiver is about -9.2 dBm for a BER of less than 10-12(with a PD responsivity of 0.53 A/W). The recovered data jitter at the demultiplexer output is about 1.74 ps (rms). Implemented in a TSMC 40 nm CMOS process, the core area of the receiver chip is only 0.09 mm2. It demonstrates an energy efficiency of 2.4 pJ/bit for the entire receiver at 20 Gbps operation.

Power amplifier (PA) is one of important components in wireless communication system. However, its non‐linear and memory characteristic cause harmful distortion, which significantly decreases the power efficiency and wastes electronic energy since the power of PA needs back off. To overcome the non‐linear and memory problems, a novel method based on distortion‐characteristic estimation algorithm is developed in this study. The main innovation of this study is manifested in two aspects: first, the authors use well designed training signals to estimate the distortion characteristic of the PA; second, a novel PA characteristic estimation algorithm is developed in order to calculate the optimal state of the ideal predistorter that behaves like the inverse characteristic of PA theoretically. Since this novel method does not require the error between original signals and feedback signals, it can avoid the significant errors caused by the time mismatch between source signals and feedback signals, and can increase the power efficiency of the PA. The simulation results validate the performance increase and the synchronisation‐error immunity over the existing simplified filter look up table method.

A low-jitter digitally controlled oscillator (DCO) with multiphase differential outputs and good linearity is presented. The DCO is composed of four differential delay cells and can achieve linear tuning over a wide frequency range. The proposed fully differential delay cell comprises logic cells in standard library and varactors. The measured rms jitter and pk-pk jitter from 2.5-GHz carrier are 2.827 and 29 ps, respectively. The power consumption is 6 mW from a 1.2 V supply. An experimental prototype is designed using 65-nm CMOS technology, and the chip area is 156 μm × 92 μm2.

An energy harvester and ultra-low-voltage audio driver to mechanically stimulate tympanic membrane (TM) transducer is presented. By wirelessly optical signal and power transfer, the audio driver is able to directly drive the actuator on the TM to improve sound quality while avoiding occlusion effects. The measured THD+N is 0.4% over the audio bandwidth with modulation index of 0.4, and maximum power conversion efficiency is 24.7%. The core circuits dissipate 1.66mW from 0.6 V through optical power transfer. Fabricated in TSMC 90 nm CMOS technology, the chip size is 0.88×0.84mm2.

A 40 Gbps optical receiver analog front end integrating a trans-impedance amplifier (TIA) and a limiting amplifier is presented. To achieve wide band operation, nested feedback TIA and interleaving post amplifier with split series-peaking are proposed in this design. This receiver provides the transimpedance of 92 dBOhm, input-referred noise of 14 pA/√Hz, −3dB bandwidth of 35 GHz, and 800mVppdifferential output voltage swing. The total power dissipation is 168 mW from 1.2-V supply. Fabricated in a 65 nm CMOS technology, the chip size is 0.825mm2.

This paper presents the design of a 14 bands CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system. Based on a single phase-locked loop and two-stage frequency mixing architecture, it alleviates harmonics mixing and frequency pulling to diminish spurs generation. Also, only divide-by-2 dividers are needed in the feedback path of the PLL. Thus more precise I/Q sub-harmonics can be derived for the SSB mixer in the 14 bands carrier generation. The image spurs are suppressed below -45 dBc and improved by more than 22 dB incorporating with I/Q calibration. Implemented in a 0.18-μm CMOS technology, this chip drains 65 mA from a single 1.8 V supply. The chip size is 2.5 by 2.2 mm2providing 14 bands I/Q phases.

This paper presents an analog layout migration methodology to quickly provide multiple layouts while keeping similar or better circuit performance. Unlike previous works that often generate a single layout that has exactly the same topology with the original layout, this new migration algorithm is able to provide results with different aspect ratios. First, various placement constraints, including topology, matching, and symmetry, are extracted from the original layout. The extracted constraints are hierarchically stored into a topology slicing tree. Placement is performed from the bottom tree nodes to the root tree node. In each tree node, multiple placements for the subtree are recorded. All possible placements under the constraints are recorded in the root node. This algorithm has been successfully applied to a variable gain amplifier and a folded cascode operational amplifier migrating from UMC 90nm to UMC 65nm. The experimental results validate that our approach can provide reasonable layouts, even a better result almost in no time.

A 2.4 GHz reference-less single chip wireless receiver for 1 Mbps QPSK demodulation is presented. The receiver accomplishes LO carrier recovery and data demodulation directly from the received RF signal without resort to resonator based reference, such as crystal oscillator. Integrating LNA, mixer, LO carrier recovery loop, post amplifier, and digital demodulator on a single chip, the total power consumption is 20.4 mW. The measured phase noise from a recovered carrier at 2.432 GHz is about -112 dBc/Hz at 1 MHz offset. The chip size is 1.75 × 1.55 mm2.

A 10-Gb/s 90-dBOmega optical receiver analog front-end (AFE), including a transimpedance amplifier (TIA), an automatic gain control circuit, and a postamplifier (PA), is fabricated using a 0.18-mum CMOS technology. In contrast with a conventional limiting amplifier architecture, the PA is consisted of a voltage amplifier followed by a slicer. By means of the TIA and the PA codesign, the receiver front-end provides a -3-dB bandwidth of 7.86 GHz and a gain bandwidth product (GBW) of 248.5 THz-Omega. The tiny photocurrent received by the AFE is amplified to a differential voltage swing of 900 mVppwhen driving 50-Omega output loads. The measured input sensitivity of the optical receiver is -13 dBm at a bit-error rate of 10-12with a 231-1 pseudorandom test pattern. The optical receiver AFE dissipates a total power of 199 mW from a 1.8-V supply, among which 35 mW is consumed by the output buffer. The chip size is 1300 mumtimes1796 mum

This paper presents the design of a low power programmable PRBS generator and a low noise clock multiplier unit (CMU) for 10 Gbps serdes applications. The PRBS generator is capable of producing 2/sup 7/-1, 2/sup 10/-1, 2/sup 15/-1, 2/sup 23/-1, and 2/sup 31/-1 b test pattern according to ITU-T recommendations. High speed and low power operations of the PRBS generator are achieved by 16 paths parallel feedback techniques. The measured jitter of the CMU is only 3.56 ps/sub rms/, and the data jitter at the PRBS output is mainly determined by the CMU. Implemented in a 0.18 /spl mu/m CMOS process, the power dissipation for PRBS generator is only 10.8 mW, and the CMU consumes about 87mW.