Demo Data from EDBT 2026 / reviewers in the wild / expert
Avigail Orni
dblp:74/7082
· DBLP profile ↗
4ranked-venue papers
0as first author
0since 2021 · last 2015
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 2Theory of computation · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
1 paper |
Automated reasoning and model checking · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 77% Processor architecture and microarchitecture · 23% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
hardware verification |
0.1 | 1 | 2011 | TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overhead · DAC 2011 |
Automated reasoning and model checking
causality-based explanation |
0.1 | 1 | 2009 | Explaining Counterexamples Using Causality · CAV 2009 |
Automated reasoning and model checking › model checking
counterexample explanation |
0.1 | 1 | 2009 | Explaining Counterexamples Using Causality · CAV 2009 |
Methods — techniques the papers use, named apart from their topics
trace buffer compression · 0.1causality analysis · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2015 | Designer-level verification: an industrial experience story
Stephen Bergman, Gabor Bobok, Walter Kowalski, Shlomit Koyfman, Shiri Moran, Ziv Nevo, Avigail Orni, Viresh Paruthi, Wolfgang Roesner, Gil Shurek, Vasantha Vuyyuru |
DATE | 7 |
| 2012 | Explaining counterexamples using causality
Ilan Beer, Shoham Ben-David, Hana Chockler, Avigail Orni, Richard J. Trefler |
Formal Methods Syst. Des. | 4 |
| 2011 | TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overheadabstractThis paper presents TAB-BackSpace, our novel scheme to provide the effect of an unlimited-length trace buffer with no on-chip overhead beyond the existing debug logic. We present the theoretical foundation of our work, simulation studies on how we reduce the possibility of computing an erroneous trace, and results from the bring-up lab on real silicon of an IBM POWER7 processor, where TAB-BackSpace computes almost a thousand additional cycles of trace buffer information without any additional on-chip overhead. Flavio M. de Paula, Amir Nahir, Ziv Nevo, Avigail Orni, Alan J. Hu |
DAC | 4 |
| 2009 | Explaining Counterexamples Using Causality
Ilan Beer, Shoham Ben-David, Hana Chockler, Avigail Orni, Richard J. Trefler |
CAV | 4 |