Demo Data from EDBT 2026 / reviewers in the wild / expert
Gaurav Veda
dblp:74/7123
· DBLP profile ↗
7ranked-venue papers
0as first author
1since 2021 · last 2025
0000-0001-5052-1910ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 6 · 1 since 2021Artificial intelligence and machine learning · 1Databases, data management, data science and information retrieval · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% | |
| Databases, data mining, and information retrieval
1 paper |
Web and social media mining · 67% Information retrieval · 33% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
fault diagnosis |
0.4 | 1 | 2020 | Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Electronic design automation
hardware verification and test |
0.4 | 1 | 2020 | Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Electronic design automation › hardware verification and test › fault diagnosis
intermittent fault diagnosis |
0.4 | 1 | 2020 | Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Electronic design automation › hardware verification and test › fault diagnosis › logic diagnosis
scan chain diagnosis |
0.4 | 1 | 2020 | Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Web and social media mining › social media analysis
blog analysis |
0.1 | 1 | 2009 | Turning down the noise in the blogosphere · KDD 2009 |
Information retrieval
retrieval models |
0.1 | 1 | 2009 | Turning down the noise in the blogosphere · KDD 2009 |
Web and social media mining
social media analysis |
0.1 | 1 | 2009 | Turning down the noise in the blogosphere · KDD 2009 |
Methods — techniques the papers use, named apart from their topics
multistage inference · 0.4artificial neural network · 0.4affine group derivation · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon DefectsabstractDiagnosis simulation based on stuck-at faults cannot expose all chain diagnosis problems because silicon defects don’t behave exactly as stuck-at faults. For chain failures, the fault effect can be activated during scan shift cycles and capture cycles in scan test patterns. The activation conditions of silicon defects are generally more complex and do not activate the fault effect in all cycles. To accurately estimate diagnosis coverage during chain diagnosis simulation, this paper proposes using distinguishing bits. Distinguishing bits, which are simulation-failing bits of one fault but not simulation-failing bits of another fault, are used in this paper to distinguish each silicon defect from others. The chain diagnosis quality of silicon defects can be improved by increasing the distinguishing bits of all scan cell faults. Specific diagnosis test patterns are proposed to increase the number of distinguishing bits of each fault. If the diagnosis test patterns cannot be created, adaptive diagnosis points are proposed to modify the designs to facilitate the creation of these diagnosis test patterns. Wu-Tung Cheng, Artur Stelmach, Jakub Janicki, Preston McWithey, Gaurav Veda, Szczepan Urban, Jayant D'Souza |
ITC | 6 |
| 2020 | Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning ProcessabstractDiagnosis of intermittent scan chain failures still remains a hard problem. In this article, we demonstrate that the use of artificial neural networks (ANNs) can lead to significantly higher accuracy. The key of this method is a multistage process incorporating ANNs with gradually refined focuses. During this process, the final fault suspect is elected through multiple rounds of ANN inference, instead of just one round. At each stage, identification of a proper Affine Group, used as the “candidate set of scan cells for the next round of ANN inference,” will influence the final diagnostic accuracy. Thus, we propose a validation-based learning procedure for Affine Group derivation to further boost the final diagnostic accuracy. The experimental results on benchmark circuits have shown that this method is, on the average, 17.46% more accurate than a state-of-the-art commercial tool for intermittent stuck-at-0 faults. Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang 0005, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 5 |
| 2019 | Improving scan chain diagnostic accuracy using multi-stage artificial neural networksabstractDiagnosis of intermittent scan chain failures remains a hard problem. We demonstrate that Artificial Neural Networks (ANNs) can be used to achieve significantly higher accuracy. The key is to take on domain knowledge and use a multi-stage process incorporating ANNs with gradually refined focuses. Experimental results on benchmark circuits show that this method is, on average, 20% more accurate than a state-of-the-art commercial tool for intermittent stuck-at faults, and improves the hit rate from 25.3% to 73.9% for some test-case. Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang 0005, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng |
ASP-DAC | 5 |
| 2019 | Deep Learning Based Test Compression AnalyzerabstractWith the increase in design complexity and test data volume, compressed tests together with on-chip test decompression hardware such as Embedded Deterministic Test (EDTTM) are widely used in industry in order to reduce test cost. One of the challenges of such Design-for-Test (DFT) technology is to determine a set of optimal parameters such as the number of scan chains, scan channels, power budget, etc. such that it can reach the highest test coverage with a minimum amount of test data volume whilst satisfying various other constraints. To achieve the optimal compression configuration quickly, in this work deep learning technology based on Tensorflow is explored to estimate the test coverage and the data volume for a design when employing EDT under a given set of circuit parameters. Based on the estimated data, the optimal test architecture is also predicted, yielding a more efficient approach compared to the currently used trial-and-error methods. To demonstrate the advantages of our deep learning approach over the currently used utility, we present experimental data for eight industrial designs. Cheng-Hung Wu, Yu Huang 0005, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar M. Reddy, Chun-Cheng Hu, Chong-Siao Ye |
ATS | 5 |
| 2019 | A supervised machine learning application in volume diagnosisabstractVolume diagnosis has been used effectively to identify systematic defects for yield learning. Root cause deconvolution (RCD), an unsupervised machine learning technique which uses volume diagnosis data, has proven very effective for identifying root causes. As we march towards more advanced technology nodes, defects have more complicated behaviors rendering some model parameters used in RCD are not precise enough to be effective. In this paper we use a supervised machine learning technique to accurately learn these model parameters from training data. Controlled experiments using simulation data on several industrial designs show that our approach improves RCD accuracy. We also demonstrate that the approach correctly predicts 71% of the systematic defects in 21 cases validated by physical failure analysis of real silicon, which is a significantly better result compared to using the original parameters. Gaurav Veda, Wu-Tung Cheng, Huaxing Tang, Neerja Bawaskar, Sudhakar M. Reddy |
ETS | 2 |
| 2018 | Special session on machine learning for test and diagnosisabstractThe special session focuses on using Machine Learning (ML) techniques on different applications in test and diagnosis. The first contribution discusses how to close the gap between working silicon and a working system by using ML. The second presentation then talks an alternative ML view and its various applications such as functional verification, Fmax prediction, and production yield optimization. The last presentation discusses using supervised ML on volume diagnosis to further improve the accuracy of identifying root causes. Krishnendu Chakrabarty, Li-C. Wang, Gaurav Veda, Yu Huang 0005 |
VTS | 3 |
| 2009 | Turning down the noise in the blogosphereabstractIn recent years, the blogosphere has experienced a substantial increase in the number of posts published daily, forcing users to cope with information overload. The task of guiding users through this flood of information has thus become critical. To address this issue, we present a principled approach for picking a set of posts that best covers the important stories in the blogosphere. Khalid El-Arini, Gaurav Veda, Dafna Shahaf, Carlos Guestrin |
KDD | 2 |