An accurate metric for the time step control in the power device transient simulation is proposed. This metric contains an exponential term of the dominant time constant of the whole device structure derived from the matrix exponential term of the linearized device state equation. The proposed metric allows larger time step widths than the conventional metric of second order approximation of the local truncation error. It focuses on the dominant part of the transient response and its truncation error approximation is more accurate. In the transient device simulation, box integration method and backward Euler method are used for spatial and temporal discretization, respectively. The discretized nonlinear device equations are solved by using Newton iteration whose initial guess is given by the approximated solution of the linearized device state equation by using the dominant time constant. Total calculation time of the transient simulation of a silicon power DMOSFET by using the proposed method decreases down to 27% of that by the conventional method with keeping the current accuracy of the dominant transient response.

The temperature-independence point (TIP) of the drain current for MOS transistors in a 0.1 /spl mu/m-scale pocket-implant technology is gate-length (L/sub g/) dependent and has different magnitudes for n-MOSFET and p-MOSFET. Circuits such as ring-oscillators have a TIP, lying between the values for nand pMOSFET. The circuit TIP Is close to the n-MOSFET TIP for long L/sub g/ and gets closer to the p-MOSFET TIP for short L/sub g/. The reason is the different temperature dependence of electron and hole mobility as a function of L/sub g/. Due to the high field effect, oscillation periods of ring-oscillators with short L/sub g/ hardly improve, when the supply voltage is raised beyond the TIP. Therefore, an advantageous supply-voltage (V/sub DD/) choice for pocket-implant technologies is near the TIP of circuits, allowing a favorable combination of short switching delay and minimized temperature dependence. By designing the V/sub th,p/ closer to V/sub th,n/, not only the low power dissipation, due to the reduction of the TIP, but also the suppressed TIP fluctuation can be realized.

Abstract — We propose a method of correlating circuit performance with technology fluctuations during the circuit-design phase. The method employs test circuits sensitive for technology fluctuations and a circuit simulation model which enables to interpret the correlation. We validate our proposal with a cascode-current-source test circuit and the driftdiffusion MOSFET model HiSIM. The chosen test circuit allows to separate intra-chip and inter-chip technology fluctuations and to correlate these fluctuations with circuit-performance fluctuations. One important result is that intra-chip fluctuations increase faster than inter-chip fluctuations with decreasing gate length. Quantitative modeling with HiSIM reveals random fluctuation of the effective gate length as the most likely origin for these findings. I.

An approach to computing the time response of an arbitrary 3-D interconnect structure based on asymptotic waveform evaluation (AWE) is introduced. It has been implemented in a software tool called 3DAWE. To facilitate the application of AWE to a 3D RC mesh network model, the AWE formulation is rederived based on a nodal analysis approach. The ICCG matrix solver has been successfully applied in 3DAWE. It is shown that the typical transient response of a reasonably large 3D RC network can be obtained within a few minutes on a 15-MIPS computer using this program.>