Demo Data from EDBT 2026 / reviewers in the wild / expert
Stanislavs Golubcovs
dblp:74/7914
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 2013
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Interconnection networks and networks-on-chip · 56% Integrated circuit design · 44% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Interconnection networks and networks-on-chip › arbitration
arbiter design |
0.2 | 1 | 2013 | Concurrent Multiresource Arbiter: Design and Applications · IEEE Trans. Computers 2013 |
Integrated circuit design
asynchronous circuit design |
0.2 | 1 | 2013 | Concurrent Multiresource Arbiter: Design and Applications · IEEE Trans. Computers 2013 |
Methods — techniques the papers use, named apart from their topics
tiled scalable architecture · 0.2asynchronous circuit design · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | Concurrent Multiresource Arbiter: Design and ApplicationsabstractThis paper presents a novel type of asynchronous arbiter that allocates M interchangeable resources among N clients. This arbiter enables the concurrent utilization of multiple resources and is a useful device in various load-balancing circuits. Dedicated request signals from the resources and the clients are used in pairs to form each new grant. The 2 × 2 arbiter is examined as an accessible special case of the N × M arbiter. A concurrent implementation is compared to fully sequential design. It is shown that the sequential design can be more practical when the time between a grant and the withdrawal of the initial request is small. The concurrent design provides higher performance in a system with a longer resource utilization time. A scalable tiled structure is developed to extend the arbiter structure beyond 2 × 2 to support N clients and M resources. Models and subsequent implementations of the tiles are presented. The tiles can be repeated without the use of additional connecting logic, enabling the construction of arbiters of larger sizes. Several examples demonstrate the usage of the arbiter. Stanislavs Golubcovs, Delong Shang, Fei Xia 0001, Andrey Mokhov, Alexandre Yakovlev |
IEEE Trans. Computers | 1 |