This paper presents NetTLM-DSE, a novel framework for exploring the design space of layer-pipeline spatial mapping (LP-SM) for a large-scale accelerator network based on SystemC transaction-level modeling (TLM). In detail, the proposed SystemC-TLM simulator, NetTLMSim, is used to predict the network delay and optimize the mapping of deep neural network (DNN) layers to multiple accelerator cores. Conventional analytical delay models fail to accurately predict the delay of a large-scale accelerator network because of lack of the ability to capture the dynamic traffic of an accelerator network such as network contention. Such inaccurate delay prediction makes it difficult to find the optimal or near-optimal LP-SM in the corresponding design space exploration (DSE). In contrast, NetTLMSim reduces the prediction error by up to 52.8% through its cycle-accurate modeling of dynamic traffic in accelerator networks. When applied to the DSE for Transformer LP-SM, the proposed cycle-accurate simulator can find the optimal or near-optimal design options more efficiently than the conventional analytical delay models. Specifically, the proposed DSE framework, NetTLM-DSE, is shown to achieve up to 37.8% lower delay than the conventional DSE framework. In addition, a set of simulated annealing (SA) operators using dynamic traffic profiles is newly proposed to improve the efficiency of DSE. In detail, it is shown that, when applied to the DSE for Transformer LP-SM, the proposed SA operators improve the DSE speed by up to $684 \times$ over conventional SA operators. The NetTLM-DSE is open-sourced at https://github.com/SDL-KU/NetTLM-DSE

Fast Fourier transform (FFT) accelerators for IEEE 802.11ax (WiFi 6) must be designed to satisfy the stringent performance requirements specified by the standard. The design space consisting of several architectural options such as radix, memory port and loop/block pipelining is explored to optimize an FFT accelerator. Moreover, the relevant ablation study is conducted to evaluate the impact of each architectural option on the area and performance of an FFT accelerator. A commercially available high-level synthesis (HLS) tool is used to efficiently perform the design space exploration (DSE). The experimental results show that a radix-4, dual-port, fully-pipelined FFT accelerator decreases the latency by 4.7x and increases the throughput by 3x, compared to the baseline, thereby satisfying the system requirements for iterative detection and decoding (IDD) for IEEE 802.11ax. It is also shown that the proposed DSE using HLS helps to achieve a 5% improvement in area-delay product (ADP) while consuming significantly less design time than the conventional hand-coded RTL designs.

A new system-level simulator, eF2lowSim, is proposed to estimate the bit-accurate and cycle-accurate performance of eFlash compute-in-memory (CIM) accelerators for convolutional neural networks. The eF2lowSim can predict the inference accuracy by considering the impact of circuit nonideality such as program disturbance. Moreover, the eF2lowSim can also evaluate the system-level performance of dataflow strategies that have a significant impact on hardware area and performance of eFlash CIM accelerators. The simulator helps to find the optimal dataflow strategy of an eFlash CIM accelerator for each convolutional layer. It is shown that the improvement of area efficiency amounts to 26.8%, 21.2% and 17.9% in the case of LeNet-5, VGG-9 and ResNet-18, respectively.

In this paper, we investigate the extension of previous work on compressed sampling receivers from mathematical abstractions and proof of concept work into a system that directly competes with more traditional receivers in standard CMOS integrated circuit technology. As developed in the literature, the Modulated Wideband Converter shows great promise as a compressed sampling receiver due to its flexibility and inherent spectral agility. We propose several modifications to the system that improve its usability and performance in real-world scenarios. Then, using standard LTE receivers as a basis for comparison, we propose a set of target specifications for the Modulated Wideband Converter, discuss the associated circuit challenges, and evaluate potential solutions that build upon prior work in integrated circuit and system design.

In this paper, the MIMO precoder selection of LTE uplink (UL) is evaluated taking into account the gain/phase variation between SRS and PUSCH. The gain/phase variation introduced by radio impairment is modeled and the impact on precoding gain is analyzed. The simulation results show that gain variation has a stronger impact on the precoding gain than phase variation. Specifically, a gain variation of 9 dB costs 5 dB in performance.

The capability of error correction codes is largely dependent on the calculation of soft decision values. In this letter, linear-dispersion (LD) code is applied to single-carrier frequency-division multiple access (SC-FDMA) and the closed-form expression of soft decision values is derived. It is shown that the calculation of soft decision values generally depends on both time and space within an SC-FDMA symbol, as opposed to single-antenna transmission. In addition, a sufficient condition to guarantee the independence from time and space is presented.

In this paper, multiple-input multiple-output (MIMO) layer shifting with cubic metric (CM) preserving precoder and downlink control signal sharing is proposed as a uplink transmission scheme for 3GPP Long Term Evolution (LTE). The design criteria for CM preserving precoder are presented and uplink precoder is designed accordingly. By sharing MCS (modulation and coding scheme) and/or HARQ (hybrid automatic repeat request) among codewords, downlink control signal sharing reduces the control signal overhead at the expense of performance degradation, which motivates this paper. The proposed MIMO layer shifting on a per SC-FDMA (single-carrier frequency division multiple access) symbol basis eliminates the discrepancy of channel quality among codewords, and thus improves the performance in the presence of MCS and/or HARQ sharing. Simulation results show that layer shifting is beneficial to both minimum mean square error (MMSE) and successive interference cancellation (SIC) receivers.

A novel CSI-aided demapping method for dual-carrier modulation (DCM) is proposed for multiband-OFDM systems. The proposed method utilizes the channel state information (CSI) to calculate the soft decision values, which are given by the approximate log-likelihood ratio (LLR). In this paper, it is shown that the soft decision values are given as the differences between two squared Euclidean distances. By reducing the noise-amplifying effect, the proposed method improves the error performance of conventional methods, by a signal-to-noise-ratio (SNR) of 3dB in the presence of channel estimation error and quantization noise. The VLSI architecture suitable for this method is also proposed, verifying that the performance gain comes with a slight increase of hardware complexity.

Since finding the nearest point in a lattice for multi-input multi-output (MIMO) channels is NP-hard, simplified algorithms such as sphere decoder (SD) have been proposed. List sphere decoder (LSD), which is a modified version of SD, allows soft information to be extracted for channel decoding and iterative detection/decoding. In this paper, recently proposed efficient methods for reducing the computational complexity of SD and LSD with depth-first tree searching are summarized. Numerous simulations have been carried out and comparison has been made based on the average number of processing cycles. We also present two efficient schemes which can decrease hardware complexity without significant performance degradation, restricted list updating in LSD and restricted node storing at each tree level.

A probabilistic list sphere decoding (LSD) is proposed for LDPC-coded MIMO-OFDM systems. By confining the search to channel-adaptively chosen promising candidate groups, our proposed probabilistic LSD evaluates the more promising candidates earlier in the search, while retaining efficient implementation of the depth-first LSD. Simulation results show that, the proposed LSD significantly improves the error performance for constrained throughput, or increases the throughput for a fixed bit error rate. The proposed LSD can be implemented by simply adding special hardware blocks that perform preprocessing and control the tree traversal. The K-best search algorithm enables efficient implementation of the preprocessing.

Since finding the nearest point in a lattice for multi-input multi-output (MIMO) channels is NP-hard, simplified algorithms such as a sphere decoder (SD) have been proposed. With simple modification of SD, a list sphere decoder (LSD), soft information can be extracted for channel decoding and iterative detection/decoding. However, generating such information increases the computational complexity for selecting a specific number of candidate lattice points. In this paper an efficient pipelined VLSI architecture for LSD is presented and its complexity is analyzed. The architecture is constructed with three pipeline stages, two stages for metric calculation units (MCU) and one stage for metric enumeration unit (MEU). It also has three storage units and list units for three successive input MIMO vectors. The pipeline can increase the operating clock frequency and keep one-node-per-cycle policy, so that the average throughput can enhance according to the increment of the clock frequency.

An efficient probabilistic sphere decoding (SD) architecture, which applies a probabilistic search algorithm to the depth-first SD architecture, is proposed for multi-input multi-output (MIMO) systems. The proposed architecture evaluates the more promising candidates earlier in the search while retaining hardware efficiency of the depth-first SD architecture by adding special hardware blocks. The architecture either improves the error performance or increases the throughput of the state-of-the-art depth-first SD architecture significantly.