A Goldschmidt divider implemented with semiconductor quantum-dot cellular automata (QCA) is described. Most Goldschmidt dividers use a state machine for control, but state machines are difficult to implement in QCAs due to the long delays between the state machines and the computational circuits to be controlled. To resolve this problem, a data tag method is used. The data tags travel with the data and local tag decoders generate control signals. Since each datum has a tag, pipelining can be employed to increase the throughput. Using the new architecture, fixed-point Goldschmidt dividers are implemented with QCA technology.

A new method to implement faster than quadratic convergence for Goldschmidt division using simple logic circuits is presented. While the approximate quotient converges quadratically in conventional Goldschmidt division, the new method achieves nearly cubic convergence. Although division with cubic convergence has been regarded as impractical due to its complexity, the proposed method reduces the logic complexity and the delay by using an approximate squarer with a simple logic implementation and a redundant binary Booth recoder. It is especially effective in a system that already has a radix-8 multiplier. As a result, the effective area for the reciprocal table can be reduced by 25.4%. The proposed method has been verified by SystemC and Verilog models. The final results are confirmed by simulation with both random double precision numbers and an exhaustive suite of 17-bit test vectors.

A new rounding method to reduce the required precision of the multiplier for Goldschmidt division is presented. It applies special truncation methods at the final iteration step. This requires a minor modification to the rounding constants of the multiplier. It allows twice the error tolerance of conventional methods and inclusive error bounds. The proposed method further reduces the required precision of the multiplier by considering the asymmetric error bounds of Goldschmidt dividers where the factors are computed using a one's complement operation. As a result, the proposed rounding method allows the multiplier of a three-iteration Goldschmidt divider to be implemented using only three extra bits. The proposed method has been verified using a SystemC hardware model of the divider supporting variable precision. The validity of the error analysis is also checked via simulation. The final rounding results are checked with both 10^{10} random double precision floating-point significands and an exhaustive suite of 17-bit test vectors.