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Mingsheng Xu

dblp:75/10047 · DBLP profile ↗
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8ranked-venue papers
1as first author
8since 2021 · last 2025
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 3 · 1 first-author · 3 since 2021Artificial intelligence and machine learning · 2 · 2 since 2021Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021Theory of computation · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
5 papers
Processor architecture and microarchitecture · 45% Integrated circuit design · 39% Memory systems · 8%
Artificial intelligence
1 paper
Language models and text generation · 77% Efficient and distributed learning · 23%

Topics — the 17 heaviest of 17, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › out-of-order execution
out-of-order processor
0.912025
ATR: Out-of-Order Register Release Exploiting Atomic Regions · MICRO 2025
Processor architecture and microarchitecture
register file
0.912025
ATR: Out-of-Order Register Release Exploiting Atomic Regions · MICRO 2025
Emerging computing paradigms › beyond-CMOS computing
beyond-CMOS devices
0.812024
Progress on the program of Si-compatible two-dimensional semiconductor materials and devices · Sci. China Inf. Sci. 2024
Integrated circuit design
emerging device technologies
0.812024
Two-dimensional materials for future information technology: status and prospects · Sci. China Inf. Sci. 2024
Processor architecture and microarchitecture › instruction fetch › instruction prefetching
fetch directed instruction prefetching
0.812024
UDP: Utility-Driven Fetch Directed Instruction Prefetching · ISCA 2024
Processor architecture and microarchitecture › front-end
front-end stalls
0.812024
UDP: Utility-Driven Fetch Directed Instruction Prefetching · ISCA 2024
Memory systems › cache
instruction cache miss
0.812024
UDP: Utility-Driven Fetch Directed Instruction Prefetching · ISCA 2024
Processor architecture and microarchitecture › instruction fetch
instruction prefetching
0.812024
UDP: Utility-Driven Fetch Directed Instruction Prefetching · ISCA 2024
Integrated circuit design
optoelectronic devices
0.812024
Highly responsive broadband Si-based MoS2 phototransistor on high-k dielectric · Sci. China Inf. Sci. 2024
Integrated circuit design
semiconductor devices
0.812024
Progress on the program of Si-compatible two-dimensional semiconductor materials and devices · Sci. China Inf. Sci. 2024
Integrated circuit design › semiconductor devices › semiconductor device design
transistor design
0.812024
Two-dimensional materials for future information technology: status and prospects · Sci. China Inf. Sci. 2024
Natural language and speech › Language models and text generation
prompt tuning
0.712023
Tuning Multi-mode Token-level Prompt Alignment across Modalities · NeurIPS 2023
Processor architecture and microarchitecture
instruction-level parallelism
0.312025
ATR: Out-of-Order Register Release Exploiting Atomic Regions · MICRO 2025
Integrated circuit design
heterogeneous integration
0.212024
Two-dimensional materials for future information technology: status and prospects · Sci. China Inf. Sci. 2024
Integrated circuit design › semiconductor technology › semiconductor process technology
high-k dielectric
0.212024
Highly responsive broadband Si-based MoS2 phototransistor on high-k dielectric · Sci. China Inf. Sci. 2024
Integrated circuit design › 3d integration
monolithic 3d integration
0.212024
Two-dimensional materials for future information technology: status and prospects · Sci. China Inf. Sci. 2024
Machine learning › Efficient and distributed learning
parameter-efficient fine-tuning
0.212023
Tuning Multi-mode Token-level Prompt Alignment across Modalities · NeurIPS 2023

Methods — techniques the papers use, named apart from their topics

device fabrication · 1.5atomic region exploitation · 0.9wrong-path prefetching · 0.8material synthesis · 0.8machine learning for material growth · 0.8adaptive prefetching · 0.8optimal transport · 0.7contrastive learning · 0.7
YearPublicationVenuePosition
2025 Sharc: Simulator for Hardware Architecture and Real-time Control
abstract
Tight coupling between computation, communication, and control pervades the design and application of cyber-physical systems (CPSs). Due to the complexity of these systems, advanced design procedures that account for these tight interconnections are paramount to ensure the safe and reliable operation of control algorithms under computational constraints. This paper presents the Simulator for Hardware Architecture and Real-time Control (Sharc) to assist in the co-design of control algorithms and the computational hardware on which they are run. Sharc simulates the execution of a user-specified control algorithm on a given processor microarchitecture configuration, evaluating how computational constraints affect the dynamical properties of the closed-loop system. We illustrate the power of Sharc by examples of MPC applied to adaptive cruise control and the stabilization of an inverted pendulum. Sharc can be found at github.com/pwintz/sharc.
Paul K. Wintz, Yasin Sonmez, Paul Griffioen, Mingsheng Xu, Surim Oh, Heiner Litz, Ricardo G. Sanfelice, Murat Arcak
HSCC4
2025 ATR: Out-of-Order Register Release Exploiting Atomic Regions
Yinyuan Zhao, Surim Oh, Mingsheng Xu, Heiner Litz
MICRO3
2024 UDP: Utility-Driven Fetch Directed Instruction Prefetching
abstract
Datacenter applications exhibit large instruction footprints causing significant instruction cache misses and, as a result, frontend stalls. To address this issue, instruction prefetching mechanisms have been proposed, including state-of-the-art techniques such as fetch-directed instruction prefetching. However, our study shows that existing implementations still fall far short of an ideal system with a perfect instruction cache. In particular, up to $588.47 \%$ of potential IPC speedup of existing processors hides due to frontend stalls, and these frontend stalls are due to inaccurate and untimely instruction prefetches. We quantify the impact of these individual effects, observing that applications exhibit different characteristics that call for adaptive application-specific optimizations. Based on these insights, we propose two novel mechanisms, UDP and UFTQ, to improve the accuracy of FDIP without negatively affecting timeliness while leveraging prefetches on the wrong path. We evaluate our technique on 10 data center workloads showing a maximal IPC improvement of $16.1 \%$ and an average IPC improvement of $3.6 \%$. Our techniques only introduce moderate hardware modifications and a storage cost of 8 KB.
Surim Oh, Mingsheng Xu, Tanvir Ahmed Khan 0001, Baris Kasikci, Heiner Litz
ISCA2
2024 Highly responsive broadband Si-based MoS2 phototransistor on high-k dielectric
Ali Imran 0004, Qinghai Zhu, Muhammad Sulaman, Mingsheng Xu, Deren Yang
Sci. China Inf. Sci.7
2024 Two-dimensional materials for future information technology: status and prospects
abstract
Abstract Over the past 70 years, the semiconductor industry has undergone transformative changes, largely driven by the miniaturization of devices and the integration of innovative structures and materials. Two-dimensional (2D) materials like transition metal dichalcogenides (TMDs) and graphene are pivotal in overcoming the limitations of silicon-based technologies, offering innovative approaches in transistor design and functionality, enabling atomic-thin channel transistors and monolithic 3D integration. We review the important progress in the application of 2D materials in future information technology, focusing in particular on microelectronics and optoelectronics. We comprehensively summarize the key advancements across material production, characterization metrology, electronic devices, optoelectronic devices, and heterogeneous integration on silicon. A strategic roadmap and key challenges for the transition of 2D materials from basic research to industrial development are outlined. To facilitate such a transition, key technologies and tools dedicated to 2D materials must be developed to meet industrial standards, and the employment of AI in material growth, characterizations, and circuit design will be essential. It is time for academia to actively engage with industry to drive the next 10 years of 2D material research.
Hao Qiu 0001, Zhihao Yu, Tiange Zhao, Mingsheng Xu, Taotao Li, Wenzhong Bao, Yang Chai, Shula Chen, Hui-Ming Cheng, Daoxin Dai, Zengfeng Di, Zhuo Dong, Xidong Duan, Yuhan Feng, Jingshu Guo, Pengwen Guo, Yue Hao 0001, Jingyi Hu, Weida Hu, Zehua Hu, Ali Imran 0004, Ziqiang Kong, Bilu Liu, Chunsen Liu, Guanyu Liu, Kaihui Liu, Donglin Lu, Likuan Ma, Feng Miao, Zhenhua Ni, Anlian Pan, Haowen Shu, Quanyang Tao, Ziao Tian, Haomin Wang 0005, Yeliang Wang, Haidi Wu, Hongzhao Wu, Jiangbin Wu, Yanqing Wu, Longfei Xia, Baixu Xiang, Luwen Xing, Qihua Xiong, Jeffrey Xu, Yang Xu 0035, Yuekun Yang, Jincheng Zhang 0001, Tao Zhang 0090, Xinbo Zhang, Chunsong Zhao, Yuda Zhao, Ting Zheng, Peng Zhou 0021, Shaohua Kevin Zhou, Deren Yang
Sci. China Inf. Sci.5
2024 Progress on the program of Si-compatible two-dimensional semiconductor materials and devices
Mingsheng Xu, Deren Yang
Sci. China Inf. Sci.1
2023 Tuning Multi-mode Token-level Prompt Alignment across Modalities
abstract
Advancements in prompt tuning of vision-language models have underscored their potential in enhancing open-world visual concept comprehension. However, prior works only primarily focus on single-mode (only one prompt for each modality) and holistic level (image or sentence) semantic alignment, which fails to capture the sample diversity, leading to sub-optimal prompt discovery. To address the limitation, we propose a multi-mode token-level tuning framework that leverages the optimal transportation to learn and align a set of prompt tokens across modalities. Specifically, we rely on two essential factors: 1) multi-mode prompts discovery, which guarantees diverse semantic representations, and 2) token-level alignment, which helps explore fine-grained similarity. Consequently, the similarity can be calculated as a hierarchical transportation problem between the modality-specific sets. Extensive experiments on popular image recognition benchmarks show the superior generalization and few-shot abilities of our approach. The qualitative analysis demonstrates that the learned prompt tokens have the ability to capture diverse visual concepts.
Dongsheng Wang 0003, Miaoge Li, Mingsheng Xu, Bo Chen 0001, Hanwang Zhang
NeurIPS4
2023 High-performance one-stage detector for SiC crystal defects based on convolutional neural network
Zhiyuan Jin, Wenjing Tang, Mingsheng Xu, Xiangang Xu
Knowl. Based Syst.6