In order to reliably operate Lithium-ion battery systems at their maximum power capability, it is advantageous to track the battery electrical impedance. Direct-Current Fast Charging (DCFC) stations provide a low-cost opportunity to introduce in-situ impedance measurements through the shared use of new hardware across many users. The feasibility of DCFC-based EV battery pack impedance measurement is explored in this work. To the authors’ knowledge, this is the first published measurement and analysis of impedance data from a commercial EV dc charging plug. A custom 50 kW CHAdeMO-interface DCFC is implemented, featuring electrochemical impedance spectroscopy with 5 A perturbation current at 400V, up to 3.1 kHz. The high-voltage system impedance is measured for a prototype EV featuring a custom 27kWh battery pack, and a 2015 Nissan Leaf EV through the CHAdeMO port. It is found that while the vehicle-level impedance is significantly affected by the DCFC charging cable and internal vehicle components, battery impedance variation due to temperature can still be detected. This work motivates the future development of charger-side battery diagnostics, including 1) large-scale vehicle fleet battery health monitoring, 2) data collection for improved battery degradation modeling, and 3) direct information exchange with EVs for battery performance optimisation.

In earlier technology nodes, FPGAs had low power consumption compared to other compute chips such as CPUs and GPUs. However, in the 14nm technology node, FPGAs are consuming unprecedented power in the 100+W range, making power consumption a pressing concern. To reduce FPGA power consumption, several researchers have proposed deploying dynamic voltage scaling. While the previously proposed solutions show promising results, they have difficulty guaranteeing safe operation at reduced voltages for applications that use the FPGA hard blocks. In this work, we present the first DVS solution that is able to fully handle FPGA applications that use BRAMs. Our solution not only robustly tests the soft logic component of the application but also tests all components connected to the BRAMs. We extend a previously proposed CAD tool, FRoC, to automatically generate calibration bitstreams that are used to measure the application’s critical path delays on silicon. The calibration bitstreams also include testers that ensure all used SRAM cells operate safely while scaling V dd . We experimentally show that using our DVS solution we can save 32% of the total power consumed by a discrete Fourier transform application running with the fixed nominal supply voltage and clocked at the F max reported by static timing analysis.

Recently FPGA researchers have proposed different approaches to enable dynamic voltage scaling (DVS) for FPGAs. While the proposed approaches have shown that DVS is able to significantly reduce FPGA power consumption, most of these solutions were developed only for the soft fabric of the FPGA and hence cannot be deployed for applications that use the FPGA hard blocks such as block RAMs (BRAMs). In this work, we extend a previously proposed offline calibration-based DVS approach to enable DVS for FPGAs with BRAMs; we build testing circuitry to ensure that all used BRAM cells operate safely while scaling the supply voltage, and we develop testing procedures that are able to measure the delay of timing paths that start or end at BRAMs. We extend the CAD tool FRoC to automatically generate calibration designs with BRAM testers along with soft fabric testers to measure the actual Fmax of each application on any chip under different operating conditions; this information is stored in a calibration table that is then used when the application is running to scale the supply voltage to the minimum value that guarantees safe operation at the desired speed. Using our proposed solution, we show that we can run a discrete Fourier transform core with 32 % and 46 % power reduction compared to the conventional fixed-voltage operation at the reported F_max and at a lower clock frequency, respectively.

Dynamic voltage scaling (DVS) is one of the most effective ways to reduce integrated circuit power. However, the programmability of field programmable gate arrays (FPGAs) means that the critical paths depend on the application configured into the FPGA and this makes DVS more difficult. We propose a DVS technique that is able to determine the minimum safe Vddof any application for each FPGA chip. For each application, we create multiple calibration bit-streams that are used to generate a calibration table (CT), which stores the actual failing points of that application on a specific FPGA, under various operating conditions. This CT is used to scale Vddwhile the application is running to guarantee safe operation with minimal power consumption. We develop an automated tool (FRoC) that ensures a fast-robust-calibration of the FPGA to any application using it. FRoC makes the calibration process invisible to FPGA users, does not add any extra manual steps to the design process, and uses novel algorithms to minimize the extra flash storage requirements for calibration. Our results show that across a large suite of benchmarks the calibration process requires a geomean of less than four bit-streams and our DVS technique achieves a 33% total power reduction on two large applications.

Process variation is increasing with each successive technology node, and it has reached the point where the worst-case timing modelling employed by current FPGA CAD tools is significantly underutilizing the available silicon. Previous studies have proposed exploiting FPGA reconfigurability to reduce this underutilization using techniques such as late binding and dynamic voltage scaling. Most of the proposed solutions require the ability to measure the target application's delay on each configured chip. To accurately measure the delay of an application on a certain chip, we must measure the delay of its speed limiting paths on this specific chip. In this paper, we present a variation-aware CAD tool that automatically generates calibration bitstreams to measure the delay of any input application. Our tool identifies the statistically critical paths of the circuit and optimally selects which paths to test such that it minimizes the chances of reporting an optimistic delay, under a constraint on the number of allowed calibration bitstreams. Experimental results across a suite of benchmarks show that with one calibration bitstream we achieve 16× lower probability of reporting an optimistic delay compared to a greedy approach. With three calibration bitstreams, we reduce the probability of optimism to two chips in a million, approximately 6,000 × lower than a greedy approach.

Although dynamic voltage scaling (DVS) is a popular power reduction solution that has been widely used by processors and ASICs, it is still not commercially adopted by FPGAs. A unique feature of FPGAs that leads to challenges in adopting DVS is that the critical path and hence the minimum safe Vdddepends on the configured application. We present a robust DVS technique that solves these challenges. For each application, we generate a calibration table (CT) that stores the actual failing points of that application on a specific FPGA, under various operating conditions. This CT is used to scale Vddwhile the application is running to guarantee safe operation with minimal power consumption. We develop an automated tool (FRoC) that ensures a Fast-Robust-Calibration of the FPGA to any application using it. FRoC ensures that the calibration process is invisible to FPGA users and does not add any extra manual steps to the design process. We show that our proposed DVS technique achieves a 33% total power reduction on two large applications.

The objective of this work is to demonstrate a temperature-dependent impedance model for high-power lithium-ion polymer cells used in modern Electric Vehicles (EV). The impedance model is combined with a self-heating thermal model for system simulations, in order to predict the impact of different cell types on the overall EV performance, under real-world urban and highway drive-cycles. Measurements show that the internal resistance is almost doubled when the ambient temperature is lowered from 20° C to 5°C. This has a drastic impact on the EV's ability to satisfy the load current requirements without performance lags, and justifies the importance of the modelling approach. When operating in cold climates, it is observed that the Battery Thermal Management System (BTMS) must strike a balance between EV range and performance, as the stored energy should be optimally distributed between the propulsion and heating systems.

The objective of this work is to investigate the effect of an ultracapacitor/battery based hybrid energy storage system (HESS) in an electric vehicle (EV) prototype having a 200 km range. Global positioning system (GPS) data is used to enhance the HESS power-mix optimization in real-time, based on the relative position of stop signs and traffic signals. It is shown that the GPS information, which is already available in the car, is beneficial in managing the u-cap voltage and reducing the dynamic currents on the battery. Simulations comparing various power sharing algorithms show the superior performance of the GPS enhanced HESS control scheme, based on the experimental drive-cycle. It is shown that utilizing the GPS data in the power optimizer can reduce the battery's peak charge current by 38% compared to a standard HESS.

This paper presents a Wireless Sensor Node (WSN) architecture with solar power generation and a hybrid energy storage scheme. The WSN is composed of three key modules: Energy Harvesting, Energy Storage, and the Control/Processing unit. The harvesting module consists of a miniature 179 mW solar array and MPPT hardware. A rechargeable 350 mAh Lithium-Ion battery and an ultra-capacitor are used as the energy storage elements. The low-ESR ultra-capacitor efficiently supplies the load power, which can reach as high as 295 mW peak, while the battery provides high-density storage. These elements are interfaced through a digitally controlled bi-directional dc-dc converter, which efficiently regulates the power-flow in the WSN. Multiple sensors and circuitry are implemented to measure positional and environmental data, as well as receiving and transmitting data via RF communication. A long-term test of the WSN is conducted to demonstrate the effective system functionality.

The increasing need to incorporate complex control features in switched mode power supplies (SMPS) in a CMOS compatible environment has spurred the study of digitally controlled integrated dc-dc converters. Designers continuously examine various design considerations for the implementation of these power converters, including topology choices, digital vs. analog control scheme, power conversion efficiency optimization, advanced passive component technologies, and power transistors. This paper highlights some of our recent work on integrated dc-dc converters with a particular focus on outlining the novel features that are only possible with digital controllers. More specifically, recent advances such as segmented output stage, segmented gate driver, dead-time control, and transient suppression are reviewed.

We introduce a novel infrastructure supporting automatic updates for dynamic content browsing on resource constrained mobile devices. Currently, the client is forced to continuously poll for updates from potentially different data sources, such as, e-commerce, on-line auctions, stock and weather sites, to stay up to date with potential changes in content. We employ a pair of proxies, located on the mobile client and on a fully-connected edge server, respectively, to minimize the battery consumption caused by wireless data transfers to and from the mobile device. The client specifies her interest in changes to specific parts of pages by highlighting portions of already loaded web pages in her browser. The edge proxy polls the web servers involved, and if relevant changes have occurred, it aggregates the updates as one batch to be sent to the client. The proxy running on the mobile device can pull these updates from the edge proxy, either on-demand or periodically, or can listen for "pushed" updates initiated by the edge proxy. We also use SMS messages to indicate available updates and inform the user of which pages have changed. Our approach is fully implemented using two alternative wireless networking technologies, 802.11 and GPRS, and evaluated on real world dynamic content traces. Our evaluation explores the data transfer savings enabled by our proxy-based infrastructure and the energy consumption when using each of the two networking capabilities. Our results show that our proxy system saves data transfers to and from the mobile device by an order of magnitude and battery consumption by up to a factor of 4.5, compared to the client-initiated continuous polling approach. Our results also show even in the case where users never visit the same page twice, energy consumption is reduced by the pre-fetching and batching or our proxy system.