VLIW, multi-context, or windowed-register architectures may require one hundred or more processor registers. It can be difficult to design a register file with so many registers that meets processor cycle time requirements. We propose to resolve this problem by taking advantage of register values that are bypassed within a processor's pipeline, and supplementing the bypassed values with values supplied by a small register cache. If the register cache is sufficiently small then it can be designed to meet a fast target cycle time. We call this combination of bypassing and register caching the register scoreboard and cache. We develop a simple performance model and show by simulations that it can be effective for windowed-register architectures.

The performance of a disk system is often measured in terms of the length of the waiting line or queue of requests for each of the system's spindles. Thus it is natural to formulate and analyze queueing models of disk systems. While most disk systems have certain characteristics, such as channel interference and concurrent seeks, in common, previous analyses have always been begun from scratch, without exploiting this commonality. We introduce a general queueing model for disk systems, which incorporates the characteristics common to most disk systems, and use it in the approximate analyses of models of the IBM 2314 and 3330 disk systems. Comparisons with simulation statistics show that the approximations made are very good over a wide range of arrival rates and system parameters. We also show how to use the analytic results to investigate performance differences between devices.

This paper studies the problem of interconnecting circuit modules in microprocessor and digital system design. This problem is ever-present and has generally been handled in a heuristic manner.