A 12b analog-to-digital converter (ADC) consisting of an 8b successive approximation register (SAR) ADC, a voltage-to-time converter (VTC), and a gated cyclic Vernier time-to-digital converter (TDC) is presented. A number of design techniques including a sub-threshold delay-locked loop (DLL) with pulsed outputs to generate the clock signals of the ADC, a power/area-efficient technique to eliminate the kickback-induced errors of the comparator, a gated cyclic Vernier TDC to eliminate resolution loss at both input injection and catch, a self-resetting arbiter, and a power/area-efficient synchronous SAR are proposed. The ADC is designed in a TSMC 130 nm CMOS technology with a reduced supply voltage of 0.8 V. The simulation results of the ADC with a 7.42 kHz 400 ∼ 800 V differential sinusoidal input voltage show that at 800 kS/s, the ADC offers 59.32 dB SNDR and 9.56 ENOB while consuming 3.44 µW, yielding 1.83 fJ/conv. FOM.

A gated ring oscillator time amplifier (GROTA) featuring a well-defined programmable gain, the ability to amplify a pico-second input, an unlimited range of gain, and full compatibility with technology is proposed. The transfer characteristics of the GROTA and a time offset tuning mechanism enabling the amplification of a pico-second input are presented. The characteristics and impact of supply noise and device noise are studied. A variable-gain time integrator consisting of the proposed GROTA and a bi-directional gated ring oscillator (BD-GRO) time integrator is developed and its silicon implementation in TSMC 120 nm 1.2 V CMOS is provided with simulation results.

This paper proposes an all-digital time integrator consisting of a 9-stage bi-directional gated ring oscillator (BD-GRO) and a 16-stage bi-directional shift-register (BDSR) up-down counter. The BDGRO performs time integration whereas the BDSR counter digitizes the result of time integration. The time integrator features a low resolution of the per-stage-delay of the BDGRO, low power consumption, inherent dynamic element matching, self-digitization, and full technology compatibility. The time integrator is designed in a TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3 device models. The performance of the time integrator is assessed using simulation results.

This paper presents the principle, design, and analysis of a bi-directional gated ring oscillator (BDGRO) time integrator for time-based signal processing. The time integrator features full compatibility with technology, rapid integration, low power consumption, a virtually unlimited dynamic range, built-in dynamic element matching, and self-digitization. A detailed analysis of the impact of the imperfections of the time integrator including nonlinearity, skew, supply voltage noise, device noise, and metastability-induced gating errors is provided, supported with simulation results. The time integrator is designed in a TSMC 130 nm 1.2 V CMOS technology and analyzed using Virtuoso/Spectre with BSIM3 device models. Time integration is confirmed using simulation results in both time and frequency domains. The time integrator exhibits a clean spectrum without noticeable harmonics and consumes 0.25 mW with a gain of 15.48 dB at 20 MS/s.

The metastability of catch-detect DFFs in Vernier time-to-digital converters (TDCs) causes the DFFs to yield an erroneous, reducing the resolution of the TDCs. In this paper we propose a new metastability correction technique for true single-phase clock (TSPC) D flip flops (DFFs) in catch detection of Vernier TDCs. The proposed technique eliminates the metastability-induced errors of catch-detect DFFs in Vernier TDCs without affecting both resolution and conversion time. The effectiveness of the techniques is validated using the simulation results of two 8-stage Vernier TDC designed in a TMSC 130 nm CMOS technology.

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively.

An 8-bit time-mode successive approximation register time-to-digital converter (SAR TDC) is proposed. The TDC achieves a high resolution and a better power/area efficiency by using a pre-skewed delay line with digital time interpolation. The impact of pre-skewing on delay and power consumption is investigated. A cascode inverter interpolation cell with improved input-output isolation is introduced. The impact of the slope of input signals on the linearity of the time interpolator is investigated. Timing errors caused by device noise are quantified. The SAR TDC is designed in a TSMC 65 nm 1.0 V CMOS technology and analyzed using Spectre with BSIM3.3 device models. Simulation results show the SAR TDC operated at 10 MS/s achieves 0.33 ps solution, 9.68 ENOB, and 0.20 pJ/conv. FOM.

A fast-locking phase-locked loop (PLL) with variable loop dynamics is proposed. The PLL employs a time amplifier (TA) with a variable gain to amplify the phase difference between the reference clock and the output of the voltage controlled oscillator (VCO). It operates by dynamically increasing the bandwidth of the PLL during locking state to speed up locking process and decreasing the bandwidth of the PLL in locked state to optimize the performance of the PLL. The insertion of the TA also reduces the time constant of the loop filter without sacrificing performance, thereby allowing the reduction of the resistance and capacitance of the loop filter subsequently their silicon and power consumption. The increased width of Up and Down pulses also enable the reduction of the current of the charge pump while achieving the same variation of the control voltage thereby lowering the power consumption. Two identical PLLs, one with the TA and the other without were designed in an IBM 0.13 μm CMOS 1.2 V technology and analyzed using SpectreRF from Cadence Design Systems with BSIM4 device models. Both critically damped and under-damped cases were investigated. Simulation results demonstrate that in the critically damped case, the lock time of the PLL with the TA is 0.42 μs while that without is 0.52 μs. In the under damped case, the lock time of the PLL with the TA is 0.30 μs while that without is 1.54 μs.

This paper presents a new time integrator for mixed-mode signal processing. The proposed time integrator consists of two time adders realized using a time-to-voltage and voltage-to-time conversion mechanism. All transistors of the proposed time integrator operate in an on/off mode, the time integrator is fully compatible with digital-oriented CMOS. The effect of nonidealities including charge injection, leakage, and jitter is examined in detail. The proposed time integrator has been designed in an IBM 130 nm 1.2V CMOS technology. Simulation results show that the time integrator provides a gain of 21 dB with a 317 kHz 30 ps peak-to-peak time input, and consumes 101.6 μW with 25 MHz sampling clock.

This paper presents a minimum jitter-based adaptive decision feedback equalizer (DFE) for 4PAM serial links. For each signal level, a dedicated sign-sign least-mean-square (SS-LMS) algorithm is employed to adjust corresponding DFE tap coefficient as per data rate and the characteristics of channels. The proposed adaptive DFE is embedded in a 2 Gbps serial link over a 12-inch FR4 channel implemented in an IBM 130 nm 1.2V CMOS technology. The link is analyzed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results demonstrate that the proposed adaptive DFE is capable of opening completely closed data eyes.

This paper presents an adaptive Decision-Feedback Equalizer ADFE utilizing a proposed hexagon eye-opening monitor for multi Gbps serial links. The adaptation process of proposed ADFE depends on the error signals which are delivered from error detection unit EDU. The EDU employs a hexagon eye-opening monitor H-EOM to detect the violations of the received data signals after the comparison with three threshold voltage levels at two sampling points. The extracted error signals are then conveyed to the input of an adaptive engine. The adaptive engine updates the feedback tap coefficients of the DFE automatically based on these error signals. The examination of the comparison of the proposed DFE architect with the adaptive DFE architect employing a rectangular eye-opening monitor R-EOM shows that the proposed architect obtained better performance for providing convergence time and voltage, and identifying jitter violations. The effectiveness of the proposed architect is validated using the simulation results of a serial link designed in an IBM 130 nm 1.2V CMOS technology.

This paper presents a new 2-D on-chip eye-opening monitor (EOM) for Gb/s serial links. A comprehensive review of the state-of-the-art of on-chip EOMs is provided and their pros and cons are investigated. A new hexagon 2-D EOM that outperforms the widely used rectangular 2-D EOMs is introduced and the implementation details are presented. The effectiveness of the proposed EOM is evaluated by embedding it in a serial link implemented in an IBM 130 nm 1.2 V CMOS technology. For the purpose of comparison, a rectangular 2-D EOM is also included in the same data link. The data link with a variable channel length and attenuation is analyzed using Spectre from Cadence Design Systems with BSIM four device models. Simulation results of the data link demonstrate that the proposed EOM outperforms the rectangular EOM by providing a tightened control of data jitter at the edge of data eyes and by eliminating unnecessary errors flagged by the rectangular EOM.

Many researchers seek for alternatives to traditional computing architectures, often placing emphasis on modeling biological systems that possess intelligence and learning capabilities. Cortical columns have emerged as a high-level unsupervised learning model for extracting independent data features in a hierarchical manner. Previous cortical models simply rely on software based techniques and neglect the actual purpose of investigating these architectures: to diverge from the conventional Von Neumann approach to an actual hardware realization of an intelligent system. This work presents the hardware realization of a cortical column system, taking several factors into consideration which were previously disregarded by software models. We introduce a Neural Spike Dual-Rail communication scheme, and a temporal pooling unit capable of detecting data distortions during training and testing. This work concludes with a study on cortical columns and their hierarchical impact on hardware resources.

This paper proposes a charge-domain quadrature down-conversion sampling mixer with improved filter functionality. An 4-path bandpass filter and a quadrature sampling mixer are integrated in a cascode architecture to minimize power consumption while providing a degree of programmability. The proposed design is applicable to heterodyne receivers for suppressing aliasing signals, large out-of-band blockers, and IF images. It also offers partial channel selection. Designed in IBM 130 nm 1.2V CMOS technology, simulation results from Spectre of Cadence Design Systems with BSIM4 device models demonstrate that the proposed design exhibits aliasing rejection of 70 dB, stop band attenuation of 60 dB while consuming current of 104μ A.

RFID technology has been widely used in logistic, automation and authentication applications, but it still has many potential issues such as the risks of privacy and security. This paper presents a novel RFID security protocol based on XTEA algorithm. Analysis of the security and privacy of this novel protocol is performed using FPGA based prototyping platform. Different attack models are implemented, and the results show that the protocol is robust and safe against major attacks. Analysis of the performance is compared with related works and shows its advantages in code size, clock cycle, communication cost and scalability.

This paper presents a new active inductor LC-tank voltage-controlled oscillator with an ultra wide frequency tuning range. The large frequency tuning range is obtained by varying the inductance of the active inductor. Two inductance tuning mechanisms, namely the wide-band tuning mechanism for coarse frequency adjustment over a large frequency range for band selection and the primary tuning mechanism for the fine frequency tuning in frequency synthesis, are introduced. The proposed oscillator was designed and implemented in TSMC-0.18 mum 1.8V 6-metal 1-poly CMOS technology. The oscillator occupies a small active area of 85 times 50 mum2. The wide-band tuning mechanism provides a frequency tuning range from 0.2 GHz to 6.5 GHz while the primary tuning mechanism provides a frequency range from 1.4 GHz to 1.7 GHz when the center frequency of the oscillator is set to 1.6 GHz. The phase noise with the VCO tuned to 1.6 GHz is -118.5 dBc/Hz at 1 MHz frequency offset.

This paper proposes a new remote frequency calibration method that allows a passive wireless microsensor to adjust the oscillation frequency of its local oscillator using a calibrating reference signal sent by its reader. The reference signal is transmitted wirelessly by the reader in the form of a modulated tone. Frequency calibration is achieved by employing an injection-locking phase-locked loop that adjusts the oscillation frequency of the relaxation oscillator of the microsensor to that of the reference signal. The hysteresis of the relaxation oscillator is created by a novel mono-stable current pulse generating circuit also proposed in this paper. The proposed remote frequency calibration system has been designed in TSMC-0.18µm 1.8V 6-metal 1-poly CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3V3 device models. The power consumption of the VCO is 525 nW while that of the system is 912 nW.

Inter-signal timing skew gives rise to reduced timing margins at the receiver and limits the data rate of parallel links. This paper proposes a new inter-signal timing skew compensation technique for parallel links with voltage-mode incremental signaling. The proposed technique employs an early/late block to detect the rising and falling edges of adjacent pulses generated at the output of comparators due to inter-signal timing skews, and subsequently to allocate the optimal sampling point of the samplers to maximize timing margins. Two delay-locked loops (DLLs) are employed to place the sampling clock to the optimal sampling position. The skew compensation range is quantified with reference of the delay range of the DLLs. The effectiveness of the proposed deskewing method is validated using a 1 Gbyte/s parallel link implemented in UMC-0.13 mum 1.2 V CMOS technology with three microstrip channels on a FR4 substrate.

This paper presents a new over-sampling sigma delta modulator for WiMAX applications using an active inductor based loop filter and CCO. The loop filter is composed of floating active inductors and offers several key advantages over its MIM capacitor loop filter counterpart including an adjustable bandwidth, an adjustable quality factor, an extremely small silicon area requirement and full compatibility with digitally oriented CMOS processes. The proposed modulator is implemented in UMC's 0.13 mum 1.3 CMOS process. The sigma delta modulator comparator and sampler are driven from a new constant-Q active inductor CCO that provides phase noise below 118 dBc/Hz at 4 GHz operation. The sigma delta modulator exhibits a signal to noise ratio (SNR) of 42 dB and a dynamic range (DR) of 63 dB at a sample rate of 2 G/s with an oversampling ratio (OSR) of 40 making it ideal for base-band sampling in WiMAX transceivers.

This paper presents the architecture and design of current-mode phase-locked loops. The proposed current-mode PLLs differ from conventional voltage-mode PLLs by replacing theirRCloop filter with aRLloop filter, eliminating the need for area-consuming capacitors. The large inductance of the current-mode loop filter is obtained from CMOS active inductors, taking the advantage of their large and tunable inductance and small silicon area. Replica-biasing techniques are used to minimize the effect of supply voltage fluctuation on the performance of active inductors. Implemented in TSMC-0.18μm CMOS technology, the simulation results of a 2.4GHz current-mode PLL demonstrate that the PLL has the lock time of 300ns approximately, dc power consumption 7.76mW, and phase noise of -110dBc at 1MHz frequency offset.

A new BPSK modulator for Bluetooth applications is presented. The proposed modulator minimizes the bandwidth of the modulated carrier by minimizing the degree of sharpness of the transactions of modulated carrier. To avoid the drawbacks of large silicon area requirement of passive spiral inductors and transformers, CMOS active transformers are developed from corresponding CMOS active inductors. They are utilized in the design of the 1.6 GHz quadrature oscillator to provide a high-quality sinusoidal output. To assess the performance of the proposed modulator, a 1.6 GHz BPSK modulator has been implemented in a TSMC-0.18μm 1.8V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3v3 device models and the simulation results are presented.

This paper presents a systematic approach to synthesize gyrator-C active transformers using MOS transistors. The self and mutual inductances of ideal and non-ideal active transformers are investigated in detailed and the intrinsic relation between the self and mutual inductances is derived. The configurations of gyrator-C active transformers with multiple primary and secondary windings are developed. Practical implementations of the proposed gyrator-C active transformers are realized in TSMC's 1.8V 0.18μm CMOS technology and their characteristics are analyzed usingSpectrefrom Cadence Design Systems with BSIM3.3 device models. Simulation results are presented.

This paper presents a new current-mode class AB transmitter with a low supply voltage sensitivity for 10 Gb/s serial links. The sensitivity of the output current to supply voltage fluctuation is achieved by operating the system in a rail-to-rail swing mode. A high speed is achieved from current-domain multiplexing and the inductive shunt peaking with active inductors. The fully differential configuration of the transmitter minimizes the effect of both common-mode disturbances and electro-magnetic interference exerted from the channels to neighboring devices. The full push-pull operation of the driver minimizes the static power consumption of the transmitter. The proposed transmitter is implemented in a 1.2V 0.13μm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. Simulation results demonstrate that the transmitter conveys a sufficiently large differential output current that is insensitive to supply voltage fluctuation at 10 Gb/s.

A new area-power efficient 4-PAM full-clock pre-emphasis CMOS transmitter for 10-Gb/s serial links is proposed. The transmitter reduces the chip area and power consumption by minimizing the number of DACs for 4-PAM pre-emphasis and the DC power consumption of each DAC. The number of DACs is set by the number of pre-emphasis taps and is independent of the number of parallel bits. The power consumption of each DAC is lowered by modulating the DC current in accordance with the level of output currents. A new full-clock multiplexing scheme is proposed to double the data rate of the widely used half-clock scheme without increasing the clock frequency. The transmitter is implemented in TSMC 0.18μm 1.8V CMOS technology and analyzed using SpectreRFM from Cadence Design Systems with BSIM3.3V transistor models and microstrip lines for channels. Simulation results are presented.

A new current-mode incremental signaling scheme for high-speed parallel links is proposed. The signaling scheme requires only N+1 physical paths for N parallel bits. It possesses the intrinsic advantages of current-mode signaling including high data rates, large signal swing, low switching noise injection, and superior signal integrity. The current-integrating front-end offers the key advantages of a low and tunable input impedance for channel termination, large bandwidth, and effective suppression of high-frequency noise coupled to the channels. Simulation results of a 4-bit parallel link implemented in a 0.13 mum, 1.2V CMOS technology demonstrate that the proposed signaling scheme is capable of transmitting parallel data at 10 Gbps

A new area efficient CMOS current-mode 4-PAM 10 Gb/s serial link transmitter is presented. The pre-emphasis of the proposed transmitter is realized by employing a delay block for each pre-emphasis tap such that the degree of each pre-emphasis tap can be tuned individually and independent of the current symbol. The multiplexing-at-input approach of the serializer ensures that the transistors of the multiplexing branches are minimum sized. A differential output current is obtained from a class AB pre-amplifier and a push-pull configured current-symbol driver and pre-emphasis drivers. The proposed transmitter minimizes the noise injected to the power and ground rails by drawing a constant current from the power supply and electromagnetic interference exerted from the channel to neighboring devices by conveying an output current of the same amplitude but opposite polarities to the channel. Implemented in a 1.2V 0.13/spl mu/m CMOS technology, the transmitter outputs a 3.5 mA peak-to-peak differential output current to the channel, consumes 19.2 mW DC power with inverter buffer chain. The current received at the far end of a 10-cm FR-4 cable has eye-width of 185 ps and eye-height of 1.21 mA.

This paper presents a new and efficient transient analysis method for mildly nonlinear circuits. The method is based on Volterra series representation of nonlinear circuits. It characterizes nonlinear circuits using a set of linear circuits called Volterra circuits. The input of the first-order Volterra circuit is identical to that of the nonlinear circuit, whereas that of higher order Volterra circuits is obtained from the response of lower order Volterra circuits. Fourier series interpolation is employed to approximate the input of higher order Volterra circuits. These circuits are analyzed using the sampled-data simulation of linear circuits for computational efficiency and the response of nonlinear circuits is obtained at equally spaced intervals of time. The accuracy of the method is. controlled by the order of Volterra and interpolating Fourier series. Various sources contributing to the error are analyzed. The method has been implemented in a computer program. Numerical results on example circuits demonstrate that the accuracy of the method is comparable to that of linear multistep predictor-corrector algorithms, but with greatly improved speed.