In this paper we discuss optimizing the interconnect power of designs implemented in FPGA platforms. In particular, we reduce the glitch power on interconnects associated with the output of functional units in a design. The idea is to activate unused flip-flops to block the propagation of glitches, which takes advantage of the abundant flip-flops in modern FPGA structures. Since the activation of additional flip-flops may cause data hazard problems, we develop several effective behavioral synthesis techniques to prevent such data hazards. We also study the optimality of our techniques. The experimental results show that on average, our methods lead to a 28% reduction in dynamic power in the Xilinx Virtex-II platform.

Factors of delay variation, such as process variation and noise effects, may cause a manufactured chip to violate the pre-specified timing constraint. In this paper, we propose a re-synthesis technique to tolerate delay variation for domino circuits. Note that the slacks of nodes along critical paths are zero; any delay addition to those zero-slack nodes worsens the final performance of a circuit. Our basic idea is to increase the slacks of nodes in the critical region by appending a redundant auxiliary subcircuit to the original circuit. The auxiliary subcircuit can cause critical paths to become false paths or imperceptible paths as stated in S. Raj et al. (2004) so as to improve the capability of delay variation tolerance. Experimental results are very encouraging.

Several factors such as process variation, noises, and delay defects can degrade the reliabilities of a circuit. Traditional methods add a pessimistic timing margin to resolve delay variation problems. In this paper, instead of sacrificing the performance, we propose a re-synthesis technique which adds redundant logics to protect the performance. Because nodes in the critical paths have zero slacks and are vulnerable to delay variation, we formulate the problem of tolerating delay variation to be the problem of increasing the slacks of nodes. Our re-synthesis technique can increase the slacks of all nodes or wires to be larger than a pre-determined value. Our experimental results show that additional area penalty is around 21% for 10% of delay variation tolerance.

Both the IR drop and EM problems require accurate analysis of maximum instantaneous current (MIC) on the power supply bus. We propose a vectorless approach to deriving a tight upper bound on MIC. We first characterize different types of signal correlation which may cause the MIC estimation to lose accuracy. We next propose theorems to identify gates which switch mutually exclusively, taking into account correlation across sequential elements (flip-flops). Note that previous research of this topic addressed on combinational circuits only. After obtaining the information of mutually exclusive switching, we then apply a graph algorithm to obtain an upper bound on MIC. In average, our results on sequential benchmarks are 212% tighter than those from iMax and 129% tighter than those from PIE based on H. Kriplani et al. (1995).