Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from EDBT 2026 / reviewers in the wild / expert

Jeffrey Y. Su

dblp:75/2759 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
0since 2021 · last 2004
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 28% Integrated circuit design · 28% Energy-efficient computing · 28%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
low-power circuit design		 0.012004
A dual-core 64b ultraSPARC microprocessor for dense server applications · DAC 2004
Energy-efficient computing › low-power design
low-power processor design		 0.012004
A dual-core 64b ultraSPARC microprocessor for dense server applications · DAC 2004
Processor architecture and microarchitecture
multicore design		 0.012004
A dual-core 64b ultraSPARC microprocessor for dense server applications · DAC 2004
Memory systems
cache design		 0.012004
A dual-core 64b ultraSPARC microprocessor for dense server applications · DAC 2004
Memory systems › memory hierarchy › cache hierarchy
l2 cache		 0.012004
A dual-core 64b ultraSPARC microprocessor for dense server applications · DAC 2004
YearPublicationVenuePosition
2004 A dual-core 64b ultraSPARC microprocessor for dense server applications
abstract
A processor core, previously implemented in a 0.25μm Al process, is redesigned for a 0.13μm Cu process to create a dual-core processor with 1MB integrated L2 cache, offering an efficient performance/power ratio for compute-dense server applications. Deep submicron circuit design challenges, including negative bias temperature instability (NBTI), leakage and coupling noise, and L2 cache implementation are discussed.
Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Ana Sonia Leon
 DAC4