As the demand for secure Internet of Things (IoT) devices increases, the need for hardware security solutions has become more critical, particularly in applications with strict power and area constraints. Thin-film transistors (TFTs) are an emerging technology, that enables the integration of complex circuits onto thin, flexible substrates offering both low-cost manufacturing and compatibility with large-area system implementations. This paper, presents, to the best of the authors’ knowledge, the first true random number generator (TRNG) based on jittered oscillator sampling, implemented in 600 nm Indium-Gallium-Zinc-Oxide (IGZO) TFT flexible integrated circuits (FlexICs) technology.The proposed TRNG achieves a throughput of 1.33 Mbits/s, an energy consumption of 4.68 nJ/bit, and occupies an area of 0.920 mm2. The TRNG showed promising results by passing 8 NIST (National Institute of Standards and Technology) randomness tests under nominal conditions. This opens new opportunities for embedding security primitives in flexible electronics, allowing for integration of hardware security in wearable electronics, biomedical devices, communication tags and other applications.

Wearable ultrasound devices for imaging and therapeutic applications demand low-power and low-area integrated circuits to interface with ultrasound transducers. In the case of ultrasound imaging front-ends, discrete time-gain compensation (TGC) simplifies gain control in ultrasound imaging (USI) ASICs, but higher gain-step resolution increases area and power dissipation, while high PSRR is needed to suppress switching noise from co-integrated HV digital circuits. This work presents a programmable-gain floating inverter low-noise amplifier (FIALNA) architecture in 28nm CMOS for low-power, wide-bandwidth USI. A thermometer-encoded variable reservoir capacitance enables fine TGC with five PVT-robust gain steps, achieving 53.6dB PSRR and an area of 0.0023mm2, an order of magnitude smaller than current PGA designs. The FIALNA dissipates 116μW and achieves 59μVrms input-referred noise, making it suitable for low-power wearable ultrasound devices.

This work presents the design and simulation of a PVT-robust x16 gain dynamic open-loop inverter-based Gm-ratio residue-amplifier for high-speed SAR-assisted pipeline ADCs. The amplifier is designed in a 28 nm standard bulk CMOS process with a regulated 0.9 V power supply and simulated across a -20°C to 85°C temperature range. It achieves a power dissipation of 1.67 mW at 1.3 GHz, corresponding to a power-speed ratio of 1.28 mW/GHz, with less than ±5% gain variation throughout all temperature corners in typical conditions.

This paper proposes a simple thermal noise cancellation technique to effectively reduce the output noise in predictive integrators. By combining a low-gain two-stage amplifier and a small auxiliary noise-cancelling capacitor, the output noise is highly attenuated. Simulation results for a classic Nagaraj-Ki predictive integrator, considering real MOS switches, demonstrate that the output thermal noise can be reduced up to 87%.

Most academic and commercial tri-dimensional (3D) parasitic resistance extraction EDA/CAD tools rely on finite element methods (FEM) and are mainly suited to digital circuitry. In analog and mixed-signal (AMS) circuits, such as power converters and radio-frequency analog front-ends, the layout structures used for the metal interconnections become much more diversified and complex. This paper proposes an EDA/CAD tool, based on an innovative methodology for 3D parasitic resistance extraction, leveraged by image processing techniques and algorithms. Some practical examples are shown to demonstrate the attractiveness of the proposed tool. Moreover, since our tool efficiently works in the domains of 2D image processing, if an extensive database of layouts is provided and enough training is carried out, advanced deep-learning techniques can be straightforwardly employed, speeding up parasitic resistance extraction in highly complex AMS layouts.

This paper presents a novel mostly passive Δ-Σ ADC using amorphous Indium Gallium Zinc Oxide (a-IGZO) thin-film transistors (TFTs). The ADC circuit consists of passive elements (resistors and capacitors), a novel dynamic comparator, a D-Flip Flop and a pseudo-CMOS BS inverter. In-house oxide TFT model is used for circuit simulations in Cadence environment. The proposed ADC results in effective-number-of-bits (ENOB) of 11.2 bits and a figure-of-merit (FOM) of 0.15 μJ/conversion step at 2 kHz sampling frequency with a 10 V power supply. This circuit would find potential applications in biomedical wearable systems, in which, the ADC is probably the most important block.

A novel temperature compensated class-AB residue amplifier based on MOS parametric amplification to be used in high-speed SAR-assisted pipeline ADCs is presented in this paper. The proposed circuit has been designed in a 28-nm standard CMOS process with a 0.9 V nominal power supply. The simulated class-AB fully-dynamic parametric amplifier has an open-loop nominal gain of 6× V/V, while dissipates 550 μW at 1 GHz. It achieves a gain variation bounded to ±3 % across the junction temperature range of -40 °C to 125 °C and it reaches a power-to-conversion-speed ratio better than 5.5 × 10-13W/Hz representing a factor of about 4 times of energy-efficiency improvement when compared with the state-of-the-art.

This paper presents a voltage controlled oscillator (VCO) using amorphous Indium Gallium Zinc Oxide (a-IGZO) thin-film transistors (TFTs). This circuit consists of a high-gain OpAmp, a comparator and a relaxation oscillator. The implemented relaxation oscillator shows a power consumption of 700 μW, when it is simulated with a supply rail of ±5 V. It shows a frequency of oscillation range from 327 to 560 Hz, when the tuning capacitance value varies from 1.6 to 5 pF. On the other hand, the VCO has a power dissipation of 1.3 mW with frequency ranging from 400 to 556 Hz with a controlling voltage from −5 to 5 V. In-house oxide TFT model is used for circuit simulations in Cadence environment. This circuit finds potential applications in large-area flexible systems, namely smart packaging, biomedical and wearable systems, which needs clocks with different frequencies.

In this work, a new two-step radio receiver architecture is proposed, fully embedding two downconversion stages into a charge-sharing (CS) SAR ADC. In order to relax the sampling rate requirements of the ADC, the input signal is firstly downconverted into a specific IF prior to quantization, by a 4-Tap time-interleaved FIR filter in a subsampling manner. Since the ADC can embed the downconversion operation, a smaller subsampling ratio can be used, thus reducing the out-of-band noise density at the output and improving performance. Circuit-level simulations demonstrate, through an 8-bit CS SAR ADC, a SNDR of 48.2 dB, THD of −56.6 dB and a SFDR of 55.1 dB, in a structure that entirely renounce conventional mixer stages. As a consequence, significant power and area savings are expected, together with improved noise and linearity performances.

This paper proposes a robust, 3-stage fully-dynamic high-gain residue amplifier for a 12-bit 80MS/s two-stage SAR assisted pipeline ADC. Parametric amplification has been used in the proposed open-loop amplifier to enhance gain. Third stage of the circuit is implemented with dynamic source followers (DSFs), which contributed to gain enhancement and also promised a robust performance against different loads and process corners. The circuit has shown a gain of 31 dB, a power consumption of 0.1 mW and an operating frequency of approximately 1 GHz from simulations. Circuit corner performance is varying almost within ±1 dB in gain and ±20% in bandwidth from the nominal. Circuit simulations have been carried out in standard 65 nm CMOS technology with a power supply of 1 V.

In this paper we present a balun low noise amplifier (LNA) in which the noise figure (NF) and power consumption are reduced by using a feedback biasing structure. The circuit is based on a conventional wideband balun LNA with noise cancellation. We propose to replace the typical current source of the CG stage by a transistor that establishes a feedback loop in that stage. This adds a degree of freedom which can be used to vary the CG transistor's transconductance, making it different from the typical value of 20 mS. Thus. we can increase the ratio between the gm of the CG and CS stages, which reduces the LNA NF, area, and power consumption, when compared with conventional circuits. Simulation results, with 65 nm CMOS transistors at 1.2 V supply, show that the LNA bandwidth is 3.4 GHz, the voltage gain is 21.8 dB, and the NF is less than 2.5 dB, with IIP3 above -5 dBm. The power dissipation is 4.3 mW. Another design, concerning linearity, has 18.6 dB voltage gain, NF below 2.9 dB and IIP3 above +3 dBm, over a 5 GHz bandwidth, with power consumption of 8.5 mW.

In this paper a four-stage self-biased voltage-controlled oscillator (VCO) is presented. The proposed ring-oscillator circuit employs a combination of dynamic-threshold-MOS (DT-MOS) and bulk-driven transistors to design low-voltage low-power VCO with high oscillation frequency. By using an auxiliary body-driven latch, the VCO achieves a wide operating frequency range from 0.88 to 1.36 GHz (more than 40% tuning range). Simulation results in a 65-nm CMOS technology shows frequency variations of 3% against temperature variation of -20 °C to 85 °C, with only 0.36 mW power consumption using a 0.7 V supply voltage.

In this paper, a new current-mode VCO-based delta-sigma modulator is presented to avoid the need to use operational-transconductance amplifiers (OTAs), which are usually the most power hungry building-blocks. The proposed hybrid structure doesn't require an explicit high-gain block in the loop filter in order to achieve high resolution with second order noise shaping. Simulation results show the proposed current-mode VCO-based ADC performance is able to achieve to SNDR/SNR of 85/85.4dB with 5MHz bandwidth with only 2dB gain in the front-end current-mode integrator. The circuit architecture uses two 4-bit pseudo-differential VCO-based quantizers, operating in parallel, and two current-steering DACs providing intrinsic dynamic element matching (DEM).

This paper presents a low-offset comparator based on n-type amorphous indium gallium zinc oxide thin-film transistors (TFTs). An a-Si:H TFT model was adapted to fit the electrical characterization data obtained for these devices. The proposed comparator comprises three pre-amplification stages, a positive-feedback analog latch and a fully dynamic digital latch. Simulation results show that the proposed circuit can work at several tens of kHz, with an accuracy of the order of 10 mV, considering a supply voltage of 10 V and a current consumption of 380 μA. Monte-Carlo simulations exhibit a 1-sigma random offset voltage smaller than 10 mV and 40 mV, respectively, with and without using autozeroing techniques.

In this paper, the current starving technique is applied to a voltage-combiners-biased symmetrical CMOS Operational Transconductance Amplifier (OTA). The proposed topology upgrade enhances the gain of the conventional topology, improves the settling time by means of enhancing its gain-bandwidth product and highly improves its energy efficiency. Simulation results of a properly optimized circuit, using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that a DC gain above 60 dB can be achieved together with a high energy efficiency (a figure-of-merit of 2200 MHz×pF/mA has been reached). The circuit was designed using a standard 130 nm CMOS technology and drains less than 0.5 mA from a 3.3 V power supply.

The manual design of Switched-Capacitor (SC) filters can be a strenuous process. This task becomes even more complex when the high gain amplifier is replaced by a low gain amplifier due to the loss of the virtual ground node, increasing the complexity of the filter's transfer function and requiring the compensation of the parasitic capacitances during the design phase. This paper proposes an automatic procedure for the design of high order SC filters using low gain amplifiers. The design methodology is based on a Genetic Algorithm (GA) using hybrid cost functions with varying goal specifications. The cost function first uses equations for the estimation of the filter's transfer function and, once the specifications are met, the filter is further optimized in order to increase its robustness to random variations. Afterwards, the gain and settling time of the amplifier is also estimated using equations and optimized against several process corners. The use of equation-based cost functions reduces the computation time, allowing the use of larger populations to cover the entire design space. Once all specifications are met, the GA uses transient electrical simulations of the circuit in the cost functions, resulting in the accurate determination of the filter's transfer function, and obtaining the final design solution within a reasonable amount of computation time.

A 0.4-V opamp-less ΣΔ modulator for biomedical applications is presented. The continuous-time (CT) 2ndorder ΣΔ modulator is realized using a passive filter topology. In order to obtain a small area, all capacitors are realized using parallel compensated depletion-mode MOSCAPs. To maximize the performance, genetic algorithms (GAs) are used to optimize the circuit for smaller area and higher signal-to-noise-plus-distortion ratio (SNDR). In the dynamic comparator, which is the only active block in the circuit, bulk-driven technique is used to obtain lower supply voltage operation. The circuit was designed in a 130 nm CMOS technology and, using a clock frequency of 2 MHz, has a bandwidth of 10 kHz to cover the most common bio-potential signals. The electrical transient noise simulation results show that the circuit achieves a peak SNDR of 58 dB and a dynamic range of 64 dB while dissipating only 410 nW, which corresponds to an energy efficiency of 32 fJ/conv.-step.

A discrete-time, switched-capacitor, MASH 2–2 4thorder ΣΔ modulator, clocked with frequency of 1 GHz, was designed in a 65 nm CMOS technology. This modulator uses passive integrators based on the ultra-incomplete settling (UIS) concept. Electrical simulations show that the modulator achieves a peak SNDR of 66.8 dB, a peak SNR of 67.7 dB, an ENOB of 10.8 bits and DR of 70dB for a signal with a bandwidth of 10 MHz, while dissipating 1.5 mW from a 1.1 V power supply voltage, indicating that, a FOM of 42.7 fJ/conv.-step can be reached.

This paper presents a new technique for the design of receiver architectures, based on the use of variable reference voltages in ADCs. The main goal is to improve the SNDR of a receiver chain when compared to traditional architectures like Low-IF or Subsampling, while performing down-conversion without the need of a Mixer block. The proposed technique takes advantage of the inherent capability of the ADC to perform the multiplication operation. High-level model simulations show that this technique is capable of improving the SNDR by about 5 dB (from 50 to 55 dB), while avoiding out-of-band noise aliasing, when compared to the referred techniques.

This paper presents a SC biquad using a simple quasi-unity gain amplifier. In sub-nanometer CMOS technologies the intrinsic gain of the transistors is low, this increases the difficulty of designing high gain amplifiers. The proposed SC filter is based on the Sallen-Key biquad and it requires only a simple low gain amplifier. A differential filter circuit, including a suitable low gain amplifier based on a fully-differential voltage-combiner is presented. The correct functionality of this circuit is validated through electrical simulations of a cascaded sixth order filter. These simulations show that for a clock frequency of 100 MHz, the frequency response of the circuit is very similar to the one of the prototype filter, with only a relative error of 1.1% in the attenuation value at the cutoff frequency.

This paper presents the design of single-stage amplifiers with enhanced DC gain without the need of using any cascode devices or any positive-feedback or feed-forward techniques. Instead, two voltage-combiners are used in replacement of the traditional tail current-source that is normally employed to bias the differential-pair. Simulation results of a properly optimized circuit example, using AIDA-C a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that DC gains above 50 dB can be achieved, together with high energy efficiency (a figure-of-merit of about 1300 MHz-pF/mA has been achieved).

This paper proposes a very simple and innovative self-biasing (SB) scheme to be applied to classic fully-differential current starved (CS) ring oscillators. Using the proposed SB circuit, it is possible to reduce, simultaneously, phase-noise and temperature sensitivity of the oscillation frequency. Simulation results from a CS and from the new SB ring oscillator, both designed in a 65 nm 1.2V standard CMOS technology are presented, to validate and demonstrate the efficiency of the proposed new self-biasing scheme. These simulation results show an improvement of about 4 dB in phase-noise (at 1 MHz offset) and, at the same time, it has been verified that the oscillation frequency changes less than 0.71 % (less than 57 ppm/°C), in the temperature range ranging from -40 to 85 °C. Moreover, due to the low noise and low power design, the proposed new SB ring oscillator achieves a simulated figure-of-merit (FOM) of -163.5 dBc/Hz, which represents 8 dB improvement, accomplishing one of the best results when compared with the state-of-the art.

In this paper we present a balun LNA with gain adjustable continuously by a voltage. The LNA is based on the combination of a common-gate and a common-source stage to cancel the noise and distortion of the common-gate stage. To obtain higher gain with the same DC voltage drop we replace resistors by PMOS transistors. This also allows continuous gain control and we show that by proper design, the effect on IIP3 and IIP2 can be neglected. With this approach, we avoid the use of switches, and the input impedance and the noise figure are not affected. Simulation results with a 130 nm CMOS technology show that the balun LNA has gain continuously tunable between 12 and 20 dB. The NF is below than 3.2 dB and the best IIP3 is higher than 0 dBm and the maximum IIP2 is 14 dBm. The total power dissipation is only 4.8 mW for a bandwidth of 5 GHz.

The design of Sigma-Delta modulators (ΣΔMs) encompasses different variables that need to be optimized together in order to maximize the performance. The design task is even more complex due to the non-linear behavior of the quantizer. Typically, a linearized model of the quantizer is used to obtain linear equations that predict the performance of the modulator, which may cause significant discrepancies between the predicted and actual behavior of ΣΔMs. To better predict the behavior of a given design solution, we propose a design methodology for ΣΔMs based on a genetic algorithm (GA) that uses both linear equations and simulations: the design solution is evaluated using the equations and, if the performance is good enough, it will be evaluated trough simulation. This hybrid cost function allows to use a GA with a large population and, therefore, obtains the best possible design solution. The hybrid cost function takes thermal noise, quantization noise, voltage swing variations and stability of the modulator into account. Furthermore, it also selects the design solution that is the most insensitive to component variations. The design of a continuous-time (CT) and a discrete-time (DT) ΣΔM are given as proof-of-concept.

This paper presents a current-mode reference shifting solution for MDAC-based ADCs that eliminates the need for external or internal reference voltage buffers, thus improving the energy efficiency and cost of the overall ADC. The solution consists of using an current source connected to the opamp's inputs, where reference shifting occurs by pulling a current through the capacitor in the opamp's feedback loop during the amplification phase, thus, emulating a voltage shift, ΔV = (IΔt)/C. The amount of necessary current, i.e., the biasing of the current source, is controlled by a replica of the converter's stage, which is followed by an integrator and a biasing circuit, all connected in a negative feedback loop. To illustrate the solution's performance, two 10 bit 100 MS/s pipeline ADCs were implemented: one based on the conventional 1.5-bit MDAC and the other based on the proposed circuit. Simulation results show the functionality of the proposed circuit and results for different wirebond inductances prove the stability and performance of the proposed solution.

The estimation of inter-channel mismatches in time-interleaved analog-to-digital converters (TI-ADCs) is a crucial step towards the compensation of output errors inherent of these converters. In this paper, we investigate a fast, accurate and low-complexity method for estimation of static gain and sample-time mismatches. The proposed technique uses a calibration signal generated on-chip through a sinusoidal oscillator inserted into a phase-locked loop (PLL), similarly as the sampling clock signal is usually generated in these high speed conversion systems. We synchronize these two PLLs to allow efficient frequency domain computations, without resorting to windowing, from which accurate estimations are feasible. We show that the accuracy of the method is not affected by nonidealities in the calibration signal as long as the calibration frequency is carefully selected.

This paper presents a novel ΔΣ circuit based on the implementation of discrete time filters using very incomplete settling. This approach allows building a ΔΣM with mostly dynamic elements thus reducing the power dissipation. A 2ndorder ΔΣM architecture, using this technique, is presented and analyzed. High-level and transient noise electrical simulations prove the validity of the concept. Electrical simulations show that the ΔΣM achieves a peak SNDR of 74.0 dB, a peak SNR of 78.6 dB and a dynamic range of 82.4 dB for a signal with a bandwidth of 300 kHz, while dissipating 204 μW from a 1.1 V power supply voltage, indicating that, a FOM of 174 dB can be reached.

This paper describes the design of a discrete-time passive Mixer/IIR filter. The use of an improved MOS Parametric Amplification leads to a moderate gain in the signal path and improved noise performance, instead of the conversion loss inherent to passive mixers. Simulation results demonstrate that, employing the proposed MPA structure based on a modified double-complementary topology with floating terminals, an improvement of over 4 dB in the overall circuit gain and up to 2 dB in the noise figure can be achieved.

This paper describes a novel two-stage fully-differential CMOS amplifier comprising two self-biased inverter stages, with optimum compensation and high efficiency. Although it relies on a class A topology, it is shown through simulations, that it achieves the highest efficiency of its class and comparable to the best class AB amplifiers. Due to the self-biasing, a low variability in the DC gain over process, temperature, and supply is achieved. A detailed circuit analysis, a design methodology for optimization and the most relevant simulation results are presented, together with a final comparison among state-of-the-art amplifiers.

In this paper we present a reconfigurable architecture for coherent built-in self-testing (BIST) of high speed IQ ADCs with moderate resolutions. The proposed system can be fully integrated with the ADC and, besides a low-jitter clock reference, no other external high quality generators are required. A locked system comprising a first phase-locked loop (PLL) with two IQ linear outputs and a second PLL with a squared output signal are proposed as well as the dedicated voltage-controlled oscillator (VCO) circuits. To illustrate the simplicity of the proposed solution, the system is designed, parameterized and simulated targeting the BIST of a 6-bit 1 GS/s ADC.

This paper presents a 14-bit 1.5 MSample/s two-stage algorithmic ADC with a power-and-area efficiency better than 0.5 pJmm2per conversion. This competes with the most efficient architectures available today namely, ΣΔ and self-calibrated pipeline. The 2 stages of the ADC are based on a new 1.5-bit mismatch-insensitive MDAC and simulations demonstrate that a THD of −79 dB and an ENOB better than 12 bits can be reached without self-calibration.

This paper describes a new digital-domain self- calibration technique for high-speed pipeline A/D converters using the internal thermal noise as input stimulus. This low- amplitude noise is amplified and recycled by the ADC itself and, due to the successive foldings, it is naturally converted into uniform noise. This noise is then used to calculate the required calibrating-codes. As an example, the calibration of a 13-bit pipeline ADC shows that the overall linearity can be significantly improved using this technique.

A low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs open-loop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive front-end sample-and-hold circuits, with dedicated switch-linearization control circuits, driven by a single clock phase. Simulated results of the ADC achieve 5.35-bit ENOB, with 20 mW and without requiring any gain control/calibration scheme.

This paper describes a variable width short pulse generator circuit for UWB radar applications, designed in a 0.18μm CMOS technology. This circuit is capable of generating pulses with a duration from 0.7 ns to 3.5 ns and an amplitude of 0.7 V with a 50 Ω load. The power supply voltage can be as low as 1.5 V and uses only 2.3 mA of power supply current.

This paper presents a framework for time-domain optimization of amplifiers employing a parallel genetic algorithm based on a message passing interface. This methodology achieves a considerable reduction in the optimization time (up to 19 times faster than a serial implementation). Increasing the processing capacity allows searching within a larger design space using complex transistors models, yielding more accurate results. The optimization, based on transient simulations, is possible due to the integration of a genetic algorithm optimizer together with the open-source simulator NGSPICE source-code.

In this paper the challenge of improving the energy-efficiency of comparators is addressed, by proposing a novel comparator structure, to be used in ultra-high-speed ADCs. In this comparator, the pre-amplification is embedded in the input switched-capacitor network by using the passive-amplification capability of MOS devices. Simulated results show that this comparator exhibits low-offset ultra-fast regeneration-time and high energy-efficiency.

This paper proposes a linearization technique for low-distortion high-swing CMOS switches based on a new method of improving the linearity of the NMOS and PMOS conductances. This method has the advantage over conventional clock-boosting techniques of avoiding large gate voltages thus reducing the stress on the gate capacitance. Simulated results of a practical sample-and-hold circuit show that, using this technique, linearity levels compatible with 12-b can be reached over the Nyquist band.

This paper discusses the use of symbolic methods applied to the design automation of SI data converters. The proposed approach is an extension of an already proved methodology, for the symbolic synthesis of linear and nonlinear data converters. This is performed by introducing SI characteristics in modified signal flow graph representation of conversion algorithms, including a new set of functional and electrical structures in the system library and, finally, defining an appropriate sizing mechanism for the new structures. The design process is here exemplified for a well known data conversion algorithm.

The optimization of high-speed pipelined ADCs employing self-calibration techniques to achieve high-resolution is discussed. Different assignments of resolution-per-stage are explored taking into account such physical limitations as thermal noise and matching accuracy in the capacitor arrays. The impact of the selected pipeline configuration in the self-calibration requirements as well as in the feasibility of the active components is analyzed. A design example is presented to demonstrate the relevant conclusions.

We describe a high-precision calibrating system where the code error voltages of a low-resolution binary-weighted capacitor-array DAC, measured against the precise code voltage references generated by a single-capacitor pulse-counting DAC, are digitized and corrected using a small subbinary-weighted capacitor-array. Computer simulation results are given to demonstrate the operation of the proposed system and the benefits that can be gained by employing gain- and offset-compensated stages.>