This paper describes research 1) to examine the impact of the Premier Award for Excellence in Engineering Education Courseware on the faculty members who developed and used award-winning courseware with their students and 2) to examine how the rewards system within higher education has changed in its valuation of innovative teaching. A case study was conducted with the faculty members who won the Premier Award from 1997 to 2012. The research team also gathered data from related populations (engineering deans and administrators; courseware end users) to provide a nuanced perspective on successful dissemination methods for courseware and on changes in the reward and recognition system in higher education.

Tablet PCs use their inherent ability to accept electronic ink (e-ink) and touch gesture input to enable users to interact with the device in a more natural way. This is especially important in learning environments where the user needs to focus on subject material rather than on the device used to record or store the subject information. Using Tablet PCs and slate devices, instructors are able to increase their effectiveness by making more dynamic presentations and by incorporating active exercises into their classroom environments. Tablet PCs also enable better and more natural note-taking by students and easier after-class review of course material and notes. Further, Tablet PCs facilitate better interaction with persons participating in classroom sessions from remote locations since they easily involve students exchanging visual descriptions of concepts with the instructor and the rest of the class. Several software packages are available to support the pedagogical needs of the university classroom as well as typical group collaborative environments. Classroom Presenter, DyKnow, WriteOn, LectureTools, and MS OneNote with the Interactive Classroom and Math Add in are examples of some of the packages that provide excellent classroom capabilities. These packages allow for a highly interactive environment with both teacher-student and student-student bi-direction real-time interaction. See www.ee.vt.edu/~igtront/tabletpc/ to download tablet PC software. Electronic textbook frameworks like VText are being developed to allow students to have an electronic textbook on their tablet or slate devices. This workshop will also explore the use of these frameworks and how they may be used to enhance student learning practices. In this hands-on tutorial faculty will receive an introduction to the use of Classroom Presenter, OneNote, Interactive Classroom, VText, VectorPad, LectureTools, and PDF Annotator. We will provide sufficient instruction for faculty to have a basic competency with the technology. Most importantly, we will show faculty various pedagogical practices that we have found helpful in using these technology tools in the classroom over the past seven years. Active learning exercises for various disciplines will be emphasized. Faculty will be tasked with developing short active learning exercises starting from the development of goals for the exercise, through the desired student interaction, and ending with the exercise assessment and improvement strategy. These active learning exercises will be targeted to students who are expected to be in the classroom as well as those who may be taking the course at extended campus locations. Exercises will be determined by the individual faculty member's disciplinary interests.

Complex defenses, such as moving target defenses, exist to help protect against threats. While these new forms of defense offer increased security, they are resource intensive and cannot be run on many new classes of network connected mobile systems. To provide security for these systems, a highly efficient defense must be used. Moving Target Defense for IPv6 (MT6D) is a network layer moving target defense that was originally designed using Python for portability to a variety of system architectures. Optimizing a moving target defense (MTD) for a specific system architecture increases performance to allow for these new defenses to be deployed in resource constrained environments. By transitioning from Python to C, and by using system specific networking features, MT6D can be successfully deployed to resource constrained network systems.

This paper describes the pedagogy, including the related international experience, being employed in the College of Engineering at a Research I university that is designed to develop competencies associated with a global engineer. In addition, the assessment methodology that has been developed to determine the extent to which students are developing the skills needed for engineering in a global context and their perceptions of a global engineer as a result of this comprehensive experience is discussed.

Tablet PCs use their inherent ability to accept electronic ink (e-ink) input to enable users to interact with the device in a more natural way. This is especially important in learning environments where the user needs to focus on subject material rather than on the device used to record or store the subject information. Using Tablet PCs, instructors are able to increase their effectiveness by making more dynamic presentations and by including active exercises into their classroom environments. Tablet PCs also facilitate better and more natural note-taking by students and easier after-class review of course material and notes. Further, Tablet PCs facilitate better interaction with persons participating in classroom sessions from remote locations since they easily involve students exchanging visual descriptions of concepts with the instructor and the rest of the class. Several software packages are available to support the pedagogical needs of the university classroom as well as typical group collaborative environments. Classroom Presenter, DyKnow, WriteOn and MS OneNote with the Interactive Classroom add-in are examples of some of the packages that provide excellent classroom capabilities. These packages allow for a highly interactive environment with both teacher-student and student-student bi-direction real-time interaction. See www.ee.vt.edu/∼jgtront/tabletpc/ to download tablet PC software. In this hands-on tutorial faculty will receive an introduction to the use of Classroom Presenter, OneNote, Interactive Classroom, VectorPad, and PDF Annotator. We will provide sufficient instruction for faculty to have a basic competency with the technology. Most importantly, we will show faculty various pedagogical practices that we have found helpful in using these technology tools in the classroom over the past seven years. Active learning exercises for various disciplines will be emphasized. Faculty will be tasked with developing short active learning exercises starting from the development of goals for the exercise, through the desired student interaction, and ending with the exercise assessment and improvement strategy. These active learning exercises will be targeted to students who are expected to be in the classroom as well as those who may be taking the course at extended campus locations. Exercises will be determined by the individual faculty member's disciplinary interests.

Are you trying to integrate interactive simulations, applets, case studies, courseware or other web-accessible materials into your classes? Where do you go to find these digital learning materials? How do you evaluate the quality of the materials you do find? Are there digital learning materials available that are aligned with the ABET criteria? Are there related resources for assessing student outcome assessments that you can use? How can you customize your course website with supplemental materials for students? How can you find a collection of self-studies that can be used to guide a department as they prepare for the ABET review process? This workshop introduces faculty who are interested in integrating digital learning materials in their courses to a set of criteria and methods useful in selecting and evaluating the quality of these materials to help achieve their course goals. The workshop focuses on the 10,000 educational resources cataloged in the Engineering Pathway digital library (www.engineeringpathway.org) and goes through the resources and tools available for faculty to use to locate, evaluate and select helpful digital learning materials to achieve their teaching and learning goals. Participants will be introduced to a general intellectual framework for integrating digital learning materials that stresses identifying the particular learning objectives and pedagogies for the use of particular materials. Participants will be introduced to two sets of evaluation criteria, those used in the Premier Award for Excellence in Engineering Education Courseware and another set that is used to guide catalogers as they register materials in a digital library. They will have a hands-on opportunity to apply these criteria to better understand the metrics for quality in digital learning materials, and how to apply these metrics to materials they are considering using to help achieve their course goals. The workshop also helps faculty locate courseware that can help satisfy the ABET criteria for evaluation. For those preparing for the ABET review process, the Engineering Pathway identifies a number of self-study that can be used to guide departments in the development of measurement instruments and processes. Lastly, the workshop will introduce new tools for student engagement with history of technology and well as current news in each discipline. Annotated textbooks with links to context-sensitive links to Engineering Pathway resources will also be explored.

The National Science Foundation (NSF) Course Curriculum and Laboratory Improvement (CCLI) Program (now the TUES program - Transforming Undergraduate Education in STEM) has produced a vast number of products and processes since its inception. The CCLI Program has fostered innovation nationwide and has worked to improve “quality of science, technology, engineering, and mathematics (STEM) education for all undergraduate students.” More often than not these innovations `remain local,' in that they are only developed and used by the initiating investigator(s) and are tied to the funding, once the initial funding ends the investigators move on. In recent years the CCLI Program has instituted a multi-stage program to encourage scale up of these innovations - extending the reach from small test-beds to national dissemination. However, this process typically recognizes and disseminates fairly large-scale innovation; the result is that most innovations developed through the CCLI Program continue to `stop where they started.' Very few CCLI projects, or their results, are integrated into daily use by the larger set of teachers and learners who might benefit from these innovations, and who should take advantage of existing projects thereby eliminating the need to regularly re-invent these works. In the spring of 2010 a workshop was held in Washington, DC in an attempt to identify the best practices for dissemination of CCLI innovations. In preparation for the workshop, approximately 2,400 CCLI award winners were surveyed to determine their practices and what they thought were indicators of successful dissemination. NSF Program Directors were also surveyed. This paper reports on the preliminary findings from the survey of CCLI Principal Investigators (PIs) and NSF's Cognizant Program Directors (PDs), and the results of panel discussions held during the meeting of invited experts in the area of STEM education and dissemination. Results indicate that the most frequently used methods of dissemination do not lead to desired outcomes. Several methods are proposed to improve access to resources and the adoption of these resources by other faculty seeking to improve teaching and learning.

The amount of data that floods today's networks is well beyond what security analysts can manage by textual means alone. In an effort to solve this problem, researchers have explored different methods of visualizing network security threats. There is little debate that humans can perceive more information visually than textually. The problem is that the majority of visualization tools in practice or proposed do not take efficient visualization techniques into consideration. As a result, it is difficult to get a high-level view of the network that facilitates rapid isolation of network attacks. We propose the Converged Security Visualization Tool (Cover-VT) to solve the efficient visualization problem. Cover-VT was designed to provide analysts with a high-level view of network threats using geographic information systems. The tool allows for rapid identification of threats by minimizing the cognitive obstacles to efficient threat location. Cover-VT includes the capability to drill-down on a node of interest for additional details and even filter out unwanted data. Cover-VT was designed with usability in mind, making it easy to comprehend while assisting the analyst in rapid threat identification. Many different security tools make up a security analyst's tool kit. Cover-VT was developed as an effective security visualization system that integrates existing security tools and network security systems.

A Tablet PC combines all the features of a regular laptop computer with a digitizing screen that interacts with a complementary electronic pen stylus. The ability to annotate on a lecture presentation using the pen stylus of the Tablet PC has attracted the attention of academics to use them as a potential tool for effective classroom instruction. Tablet PC based educational software like Classroom Presenter allows the instructor to supplement lecture material comprising of static text-based PowerPoint® slides by directly annotating on them. However, computer science and engineering classes often involve the use of non text-based lecture material like a simulation demo over which a lecturer would like to make annotations. In order to facilitate this, we present a Tablet PC-based educational tool called WriteOn1.0, the second core implementation of the WriteOn tool, developed at Virginia Tech. WriteOn allows the instructor to utilize electronic ink to annotate on top of any application window visible on the Tablet PC screen, including those that play active content like a movie or simulation, by activating its virtual transparency surface called the eVellum (electronic vellum).The ability of WriteOn to improve classroom presentation were pedagogically very useful as shown by initial classroom testing. However, in order to deploy WriteOn on large scale in classrooms as an active and effective teaching tool of choice, some aspects of the application like its operational CPU performance and the GUI called for improvement. WriteOn1.0 addresses the drawbacks of WriteOn with the introduction of features such as the dynamic eVellum, a picture-based GUI and an improvement to the operational CPU performance of the screen capture process. In this paper, we shall present how WriteOn1.0 can potentially aid in effective lecturing, especially for subject matter like programming and digital circuit design, both of which involve the use of dynamic presentation material.

Preventing exploits from compromising software applications requires a fundamental understanding of how they are being exploited, and then leveraging that understanding in the formulation of tests that reveal software application vulnerabilities. To advance that understanding this paper first presents a process/object model of computation that establishes a relationship between software vulnerabilities, an executing process, and computer system resources such as memory, input/output, and cryptographic resources. That relationship promotes the concept that a software application is vulnerable to exploits when it violates (a) constraints imposed by computer system resources or (b) assumptions made about the usage of those resources. Secondly, the process/object model also serves as a foundation for the definition of a taxonomy of vulnerabilities. That is, the computer system resources (or objects) identified in the process/object model form the categories and refined subcategories of the taxonomy. Vulnerabilities, which are expressed in the form of constraints and assumptions, are classified within the taxonomy according to these categories and subcategories. This taxonomy of vulnerabilities is novel and distinctively different from other taxonomies found in literature, and is also outlined in this paper

In this talk we describe a new software package called WriteOn. By using this software on a tablet PC, instructors can significantly improve their classroom presentations and demonstrations.

Switch-level faults, as opposed to traditional gate-level faults, can more accurately model physical failures found in an integrated circuit. However, one problem with switch-level fault simulation is that of long simulation times. This paper addresses this problem by performing fast approximate switch-level fault simulation using transistor reverse level ordering, and a novel nine-valued switch-level extension to observability. The probability of propagation of a fault from an arbitrary line of the switch-level circuit to the primary output is shown to be a function of the average node fan-in and the line's distance to primary output. Using this probability, results show one order of magnitude of complexity speed-up as compared to traditional fault simulation techniques, while maintaining good accuracy.

The MORRPH architecture is a general purpose reconfigurable processing unit, primarily designed to solve real time 2D image processing problems. Its robust architecture allows it to be used for other applications including 1D signal processing, 2D cellular automata problems, and 3D image processing. The modular, open ended architecture consists of an M/spl times/N rectangular mesh of processing elements (PEs), called the processing array. Each PE contains a single field programmable gate array (FPGA) chip and interconnections for several support chips. The FPGA chips within the PEs provide an array of logic resources, consisting of combinational logic functions, flip flops and internal chip routing resources. The types of support chips which are included in the PEs are not fixed, they are determined by the requirements of the computational task performed by the MORRPH. These memory, arithmetic, or processing support chips are specified and assembled on the MORRPH board for each particular application that is developed. Currently, the MORRPH architecture is implemented as an adapter card for the Industry Standard Architecture (ISA) computer bus. A constructed prototype with a 23 array of PEs is used in a current machine vision system to perform low level image processing functions. A significant performance increase is obtained by using the MORRPH as a preprocessing unit for the host processing computer. The MORRPH architecture is shown to be an inexpensive solution for relatively simple or very complex real time processing tasks.

Switch level faults, as opposed to traditional gate level faults, can more accurately model the physical faults found in integrated circuits. Existing fault simulation techniques have a worst-case computational complexity of O(n**2), where n is the number of devices in the circuit. A parallel hardware accelerated fault simulator (PHAFS) has been proposed in order to reduce the complexity to O(L**2), where L is the number of levels of switches encountered when traversing from output to input. The paper presents the algorithm/complexity verification as needed for the prototyping of PHAFS. The verification includes a compiled code VHDL switch level fault simulator.>

Presents a novel switch level extension to parallel fault simulation and the switch level circuit partitioning needed for parallel processing. Using 9-valued logic, reverse level ordering and a parallel hardware accelerated fault simulator, simulation complexity is reduced to O(L**2), where L is the number of levels of switches encountered when traversing from output to input.>

Signature registers are commonly used to collect test responses in built-in self-testing (BIST). If the contents of signature registers can be used as test patterns, the overall testing time can be reduced due to improved testing parallelism. Moreover, the number of extra registers for implementing BIST could be reduced. Here, the characteristics of the patterns generated by signature registers are studied through analyses as well as experiments. It is shown that the patterns generated by signature registers are rarely repeated when the number of test patterns is relatively small compared to the number of possible patterns. It is also shown that the patterns generated are almost uniformly distributed. Therefore, signature registers can be used effectively as pseudorandom pattern generators. The practicality of using signature registers as pseudorandom pattern generators is investigated by fault simulation experiments using an example circuit.>

On October 25, 1982, an X-Y addressable, 16- electrode, 4-by-4 Array, multiplexed switching electrode chip was implanted on the brain of a laboratory beagle. The purpose was to monitor the electroencephalogram (EEG) and visually evoked response (VER) data. This paper proposes a second-generation brain chip with design improvements incorporated, describes the fabrication techniques used to design a chip capable of monitoring visually evoked brain signals, and discusses the theory of operation associated with the chip. The second-generation brain chip includes self-contained power with on-board multiplexing and clocking circuits. The most significant improvement is the incorporation of analog-to-digital (A/D) converters. By using A/D converters, brain signal data can be converted at the site of implant, eliminating induced noise from analog wires used on the original chip.

Parallel computer architectures and problem solving strategies for the consistent labeling problem are studied. Problem solving factors include: processor intercommunication methods, passing order, and selection of the initial processor to receive the problem.

The majority of the work in the multiple-valued logic (MVL) area has been devoted to the study of various algebras and their properties. One such algebra was proposed by Allen and Givone. This paper is concerned with circuit realizations for this algebra. GaAs MESFET's are used as the basic circuit elements. Several five-valued circuits are proposed including a LITERAL gate, a MAX gate, and a MIN gate. The circuit analysis program SPICE is used to analyze the circuits, and the results are presented.