Demo Data from EDBT 2026 / reviewers in the wild / expert
Edgardo Duron
dblp:75/3056
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1993
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
1 paper |
Routing and switching · 61% Transport protocols and congestion control · 30% Network performance modeling · 9% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Routing and switching › switching systems
knockout switch |
0.0 | 1 | 1993 | Analysis and Implementation of a Priority Knockout Switch · INFOCOM 1993 |
Transport protocols and congestion control › congestion management
priority-aware congestion control |
0.0 | 1 | 1993 | Analysis and Implementation of a Priority Knockout Switch · INFOCOM 1993 |
Routing and switching
switching |
0.0 | 1 | 1993 | Analysis and Implementation of a Priority Knockout Switch · INFOCOM 1993 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.0analytical modeling · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1993 | Analysis and Implementation of a Priority Knockout SwitchabstractA priority knockout switch (PKS) architecture using priority based congestion control mechanisms is presented for broadband ISDN (BISDN) networks. This architecture provides the capability of assigning qualities of service to connections through per cell or virtual circuit priority mechanisms. Performance studies that use an analytical model for uniform traffic and simulation models for uniform and bursty traffic are presented. These studies indicate that the PKS architecture provides excellent cell loss rates for high priority traffic at minor expense to the low priority traffic. CMOS implementations of the switch modules that demonstrate the feasibility of the architecture are described.> Joseph B. Evans, Edgardo Duron |
INFOCOM | 2 |