Digital systems are growing in importance and computing hardware is growing more heterogeneous. Hardware design, however, remains laborious and expensive, in part due to the limitations of conventional hardware description languages (HDLs) like VHDL and Verilog. A longstanding research goal has been programming hardware like software, with high-level languages that can generate efficient hardware designs. This paper describes Kanagawa, a language that takes a new approach to combine the programmer productivity benefits of traditional High-Level Synthesis (HLS) approaches with the expressibility and hardware efficiency of Register-Transfer Level (RTL) design. The language’s concise syntax, matched with a hardware design-friendly execution model, permits a relatively simple toolchain to map high-level code into efficient hardware implementations.

In this paper, we explore the limits of Microsoft Floating Point (MSFP), a new class of datatypes developed for production cloud-scale inferencing on custom hardware. Through the co-evolution of hardware design and algorithms, MSFP achieves accuracy comparable to or better than industry standards Bfloat16 and INT8 at 3x and 4x lower cost, respectively. MSFP incurs negligible impact to accuracy (<1%), requires no changes to the model topology, and is integrated with a mature cloud production pipeline. MSFP supports various classes of deep learning models including CNNs, RNNs, and Transformers without modification. Finally, we characterize the accuracy and implementation of MSFP and demonstrate its efficacy on a number of production scenarios, including models that power major online scenarios such as web search, question-answering, and image classification.

Image segmentation is the process of partitioning an image into segments or subsets of pixels for purposes of further analysis, such as separating the interesting objects in the foreground from the un-interesting objects in the background. In many image processing applications, the process requires a sequence of computational steps on a per pixel basis, thereby binding the performance to the size and resolution of the image. As applications require greater resolution and larger images the computational resources of this step can quickly exceed those of available CPUs, especially in the power and thermal constrained areas of consumer electronics and mobile. In this work, we use a hardware tree-based classifier to solve the image segmentation problem. The application is background removal (BGR) from depth-maps obtained from the Microsoft Kinect sensor. After the image is segmented, subsequent steps then classify the objects in the scene. The approach is flexible: to address different application domains we only need to change the trees used by the classifiers. We describe two distinct approaches and evaluate their performance using the commercial-grade testing environment used for the Microsoft Xbox gaming console.

One major advantage of reconfigurable computing systems is their ability to reconfigure hardware at runtime. In this paper, we study the feasibility of achieving energy efficiency in reconfigurable computing systems (e.g., FPGAs) through runtime partial reconfiguration (PR) techniques. In the ideal scenario, we use a hardware accelerator to accelerate certain parts of the program execution; when the accelerator is not active, we use partial reconfiguration to unload it to reduce power consumption. Since the reconfiguration process may introduce a high energy overhead, it is unclear whether this approach is efficient. To approach this problem, we first analytically identify the conditions under which partial reconfiguration can reduce energy consumption. Our results indicate that the key to reduce partial reconfiguration energy overhead is to minimize the time overhead of the reconfiguration process. Based on this analysis, we design and implement a fast reconfiguration engine that achieves close-to-ideal throughput on Xilinx Virtex-4 FPGAs. Our fast reconfiguration engine utilizes a master-slave DMA pair to stream data between the SRAM and the Internal Configuration Access Port (ICAP). We experimentally verify our proposed solutions and compare our design to existing energy reduction techniques, such as clock gating. The results of our study show that by using partial reconfiguration to eliminate the power consumption of the accelerator when it is inactive, we can accelerate program execution and at the same time reduce the overall energy consumption by half.

Random decision tree classification is used in a variety of applications, from speech recognition to Web search engines. Decision trees are used in the Microsoft Kinect vision pipeline to recognize human body parts and gestures for a more natural computer-user interface. Tree-based classification can be taxing, both in terms of computational load and memory bandwidth. This makes highly-optimized hardware implementations attractive, particularly given the strict power and form factor limitations of embedded or mobile platforms. In this paper we present a complete architecture that interfaces the Kinect depth-image sensor to an FPGA-based implementation of the Forest Fire pixel classification algorithm. Key performance parameters, algorithmic improvements and design trade-off are discussed.

Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. In this paper, we present a new technique for mining temporal specifications from simulation or execution traces of a digital hardware design. Given an execution trace, we mine recurring temporal behaviors in the trace that match a set of pattern templates. Subsequently, we synthesize them into complex patterns by merging events in time and chaining the patterns using inference rules. We specifically designed our algorithm to make it highly efficient and meaningful for digital circuits. In addition, we propose a pattern-mining diagnosis framework where specifications mined from correct and erroneous traces are used to automatically localize an error. We demonstrate the effectiveness of our approach on industrial-size examples by mining specifications from traces of over a million cycles in a few minutes and use them to successfully localize errors of different types to within module boundaries.

Hardware acceleration uses hardware to perform some software functions faster than it is possible on a processor. This paper proposes to optimize hardware acceleration using path-based scheduling algorithms derived from dataflow static scheduling, and from control-flow state machines. These techniques are applied to the MIPS-to-Verilog (M2V) compiler, which translates blocks of MIPS machine code into a hardware design represented in Verilog for reconfigurable platforms. The simulation results demonstrate a factor of 22 in performance improvement for simple self-looped basic blocks over the base compiler.

The shift to multi-core processors presents a number of opportunities and challenges to different research fields, including the field of FPGA applications. This paper investigates the advantages of combining multi-core processors and reconfigurable instruction set extensions. Both our analysis and the experimental results show that these two approaches exploit different levels of parallelism. Using a case study on the Floyd-Warshall algorithm, we demonstrate that the multi-core architecture and the reconfigurable instruction set extensions complement each other. By combining these two methods together we find a win-win solution, which gives us a more efficient implementation with higher performance.

Multimedia and communication algorithms from the embedded system domain often make extensive use of floating-point arithmetic. Due to the complexity and expense of the floating-point hardware, these algorithms are usually converted to fixed point operations, or implemented using floating-point emulation in software. This study presents the design and implementation of custom floating-point units, leveraging the partial reconfiguration feature of state-of-the-art FPGAs. The custom floating-point units can be dynamically configured, loaded, and executed when needed by software applications. The system is binary compliant with the conventional MIPS architecture and the IEEE-754 standard, and supports most of the floating-point operations and relevant functionalities. Furthermore, we investigate various customization strategies and construct a set of optimized functional modules to meet different application demands or requirements. Using LINPACK as a floating-point intensive example, we replace a sequence of 25 instructions with a custom unit, and demonstrate an overall 80x application speedup.

We study whether partial reconfiguration can be used to reduce FPGA energy consumption. In the ideal scenario, we have a hardware accelerator to accelerate certain parts of the program execution. And when the accelerator is not active, we use partial reconfiguration to unload it to reduce both static and dynamic power. However, the reconfiguration process may introduce a high energy overhead, thus it is unclear whether this approach is feasible. To approach this problem, we identify the conditions under which partial reconfiguration can be used to reduce energy consumption, and we propose solutions to minimize the configuration energy overhead. The results of our study show that by using partial reconfiguration to eliminate the power consumption of the accelerator when it is inactive, we can accelerate program execution and at the same time reduce the overall energy consumption by half.

Configuration overhead seriously limits the usefulness of FPGA partial reconfiguration. In this paper, we propose a combination of two techniques to minimize the partial reconfiguration performance overhead. First, we design and implement fully streaming DMA engines to nearly saturate configuration throughput. Second, we exploit a simple form of configuration data redundancy to compress the configuration bitstreams, and we implement an intelligent ICAP controller to perform decompression at runtime. The results show that our design achieves an effective configuration data transfer throughput of up to 1.2 Gbytes/s, which actually well surpasses the theoretical upper bound of the data transfer throughput, 400 Mbytes/s. Specifically, our fully streaming DMA engines reduce the configuration time from the range of seconds to the range of milliseconds, a more than 1000-fold improvement. In addition, our simple compression scheme achieves up to 75% reduction of bitstream size and results in a decompression circuit with negligible hardware overhead.

Dynamic Partial Reconfiguration of FPGAs partitions the configurable logic fabric into static and reconfigurable regions. The reconfigurable regions' functionality changes at run time while the static regions continue unperturbed. The reconfigurable and static regions interface via fixed connection points ("bus macros"). We introduce the notion of a fitness score as the measure of how well the combined designs meet their timing constraints, subject to a given bus macro placement. We present a tool that uses design-space exploration to obtain automatic, near-optimal placements. The tool achieves 76% better fitness scores over manual placements. The location of the bus macros around a region has a noticeable impact on the timings, and we found that this is accurately reflected on our fitness score. We also found that following the accepted best design practices leads to quantifiably sub-optimal placements, underscoring the need for such a tool.

Hardware compilation flows use a high-level language like C++ or Java and translate it directly to an HDL. In this paper we propose to split the problem in two; first use a regular compiler to do the front-end processing, then use the generated machine code to produce the HDL. The MIPS-to-Verilog (M2V) compiler translates blocks of MIPS machine code into a hardware design represented in Verilog. M2V is a three-pass compiler that accepts as input basic blocks extracted from MIPS ELF images and emits synthesizable Verilog for the eMIPS dynamically extensible processor. The compiler was implemented from scratch in C++. The quality of the synthesizable Verilog output compares favorably with hand-generated code for the same input.

This paper provides an overview of the I/O subsystem of the eMIPS dynamically self-extensible processor. During execution, eMIPS can load additional logic blocks that perform a variety of functions, from adding new instructions to the base instruction set to controlling I/O pins. A dynamically loaded logic block that acts as an I/O peripheral to software is what we term an extensible I/O peripheral, and the resulting I/O subsystem an extensible I/O subsystem. Extensible I/O subsystems already exist for off-chip peripherals and busses. On eMIPS, this is now also realized to create loadable on-chip peripherals and bus interfaces. To realize the extensible I/O subsystem, we have made two changes to the existing design. First, we have added additional mechanisms for a newly loaded extensible on-chip peripheral to connect to the memory controller, to interact with system software in the discovery process, to obtain the I/O space and interrupt resources that it needs to operate correctly and finally to disconnect from it. Second, we have extended the security model to extensible on-chip peripherals and their software drivers. Privileged peripherals can request access to additional interface signals that are normally not available to non-privileged extensions. These signals allow access to physical memory, interrupt lines and I/O pins. Extensible on-chip peripherals can interact with system software via memory-mapped I/O and interrupts. Further, they can also add new I/O instructions to the processor's ISA.

A system called Agora was designed and implemented that supports the development of multilanguage parallel applications for heterogeneous machines. Agora hinges on two ideas: the first one is that shared memory can be a suitable abstraction to program concurrent, multilanguage modules running on heterogeneous machines. The second idea is that a shared memory abstraction can be efficiently supported across different computer architectures that are not connected by a physical shared memory, e.g., local area network workstations or ensemble machines. Agora has been in use for more than a year. The authors describe the Agora shared memory and its software implementation on both tightly and loosely coupled architectures. Measurements of the current implementation are also included.>

We have designed and implemented a software facility, called Agora, that supports the development of parallel applications written in multiple languages. At the core of Agora there is a mechanism that allows concurrent computations to share data structures independently of the computer architecture they are executed on. Concurrent computations exchange control information by using a pattern-directed technique. This paper describes the Agora shared memory and its software implementation on both tightly and loosely-coupled architectures.