Field-Programmable Gate Arrays have been increasingly deployed in datacenters and cloud computing infrastructure over the recent years. The most famous example, is perhaps the Microsoft Catapult project [1] , which describes a reconfigurable fabric used to accelerate the Bing web search engine. One important point highlighted by the Catapult paper is the need for performance monitoring tools that provide visibility into the state of multi-FPGA systems. Such tools are not only useful in functional debugging, but can also prove to be valuable in identifying the performance bottlenecks of the hardware.

In recent years, there has been a lot of focus on tools that help the development of FPGA applications. However, unlike the software world, there are not many FPGA tools that help analyze the performance of FPGA applications. Also, as the application platforms scale from one FPGA to many FPGAs, such as the well-known Microsoft Catapult platform, it is no longer feasible to rely on low-level FPGA debugging tools such as the embedded logic analyzers. We present Pharos, a lightweight, generic performance monitor for multi-FPGA systems. Pharos is capable of measuring unidirectional latency between multiple network-connected FPGAs, as well as measuring throughput and tracing events across the datacenter.

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The primary goal during synthesis of digital signal processing (DSP) circuits is to minimize the hardware area while meeting a minimum throughput constraint. In field-programmable gate array (FPGA) implementations, significant area savings can be achieved by using slower, more area-efficient circuit modules and/or by time-multiplexing faster, larger circuit modules. Unfortunately, manual exploration of this design space is impractical. In this paper, we introduce a design exploration methodology that identifies the lowest cost FPGA pipelined implementation of an untimed synchronous data-flow graph by combined module selection with resource sharing under the context of pipeline scheduling. These techniques are applied together to minimize the area cost of the FPGA implementation while meeting a user-specified minimum throughput constraint. Two different algorithms are introduced for exploring the large design space. We show that even for small DSP algorithms, combining these techniques can offer significant area savings relative to applying any of them alone

A synthesis environment called DSynth has been created for synthesizing high-performance pipelined circuits for FPGAs from synchronous data flow specifications. The goal of this work is to generate the minimum size circuit that meets the throughput constraint of the data flow model. To achieve this constraint efficiently, this approach relies heavily upon a library of pre-characterized pipelined circuit modules. In addition, resource sharing is used extensively to reduce the overall hardware cost

In FPGA designs significant area savings can be achieved by using slower, more area-efficient circuit modules or by time-multiplexing faster circuit modules. Unfortunately, the ability of designers to manually make such trade-offs is limited by the large number of different architectural possibilities. In order to automatically perform these trade-offs, we have developed a synthesis methodology that generates pipelined data-path circuits from a high-level data-flow specification. This methodology is capable of selecting among a variety of circuit implementations for each operation, a synthesis technique often called module selection, and generating control logic to time multiplexing each circuit module, a synthesis technique often called resource sharing. These techniques are applied together to minimize the area cost of the resulting circuit while meeting a user-specified minimum throughput constraint. We show that even for small benchmark circuits, combining these techniques can offer significant area savings relative to applying them alone.