Daniel K. Beece

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9ranked-venue papers

2as first author

0since 2021 · last 2010

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 9 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

7 papers

Electronic design automation · 86% High-performance computing · 10% Integrated circuit design · 5%

Topics — the 14 heaviest of 14, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Electronic design automation physical design	0.1	2	2010	Transistor sizing of custom high-performance digital circuits with parametric yield considerations · DAC 2010 First-Order Incremental Block-Based Statistical Timing Analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation › physical design › timing optimization statistical timing yield optimization	0.1	1	2010	Transistor sizing of custom high-performance digital circuits with parametric yield considerations · DAC 2010
Electronic design automation › circuit sizing transistor sizing	0.1	1	2010	Transistor sizing of custom high-performance digital circuits with parametric yield considerations · DAC 2010
Electronic design automation › timing analysis › static timing analysis incremental timing analysis	0.1	1	2006	First-Order Incremental Block-Based Statistical Timing Analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation › timing analysis statistical timing analysis	0.1	1	2006	First-Order Incremental Block-Based Statistical Timing Analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation timing analysis	0.1	1	2006	First-Order Incremental Block-Based Statistical Timing Analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation › hardware verification and test hardware verification	0.0	2	2003	Formal verification - prove it or pitch it · DAC 2003 SLS - a fast switch level simulator for verification and fault coverage analysis · DAC 1986
Electronic design automation › hardware verification and test formal verification	0.0	1	2003	Formal verification - prove it or pitch it · DAC 2003
High-performance computing › supercomputing bluegene/l	0.0	1	2002	An overview of the BlueGene/L Supercomputer · SC 2002
High-performance computing supercomputing	0.0	1	2002	An overview of the BlueGene/L Supercomputer · SC 2002
Integrated circuit design system-on-chip	0.0	1	2002	An overview of the BlueGene/L Supercomputer · SC 2002
Electronic design automation hardware verification and test	0.0	3	1988	SLS-a fast switch-level simulator [for MOS] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988 The IBM Engineering Verification Engine · DAC 1988 SLS - a fast switch level simulator for verification and fault coverage analysis · DAC 1986
Electronic design automation › hardware verification and test fault coverage	0.0	2	1988	SLS-a fast switch-level simulator [for MOS] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988 SLS - a fast switch level simulator for verification and fault coverage analysis · DAC 1986
Electronic design automation › circuit simulation switch-level simulation	0.0	2	1988	SLS-a fast switch-level simulator [for MOS] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988 SLS - a fast switch level simulator for verification and fault coverage analysis · DAC 1986

Methods — techniques the papers use, named apart from their topics

monte carlo · 0.1interior point nonlinear optimization · 0.1canonical first-order delay model · 0.1block-based propagation · 0.1system architecture design · 0.0performance scaling studies · 0.0event-driven simulation · 0.0compiled simulation · 0.0

Year	Publication	Venue	Position
2010	Transistor sizing of custom high-performance digital circuits with parametric yield considerations abstract Transistor sizing is a classic Computer-Aided Design problem that has received much attention in the literature. Due to the increasing importance of process variations in deep sub-micron circuits, nominal circuit tuning is not sufficient, and the sizing problem warrants revisiting. This paper addresses the sizing problem statistically in which transistor sizes are automatically adjusted to maximize parametric yield at a given timing performance, or maximize performance at a required parametric yield. Specifically, we describe an implementation of a statistical tuner using interior point nonlinear optimization with an objective function that is directly dependent on statistical process variation. Our results show that for process variation sensitive circuits, consisting of thousands of independently tunable devices, a statistically aware tuner can give more robust, higher yield solutions when compared to deterministic circuit tuning and is thus an attractive alternative to the Monte Carlo methods that are typically used to size devices in such circuits. To the best of our knowledge, this is the first publication of a working system to optimize device sizes in custom circuits using a process variation aware tuner. Daniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu	DAC	1
2006	First-Order Incremental Block-Based Statistical Timing Analysis abstract Variability in digital integrated circuits makes timing verification an extremely challenging task. In this paper, a canonical first-order delay model that takes into account both correlated and independent randomness is proposed. A novel linear-time block-based statistical timing algorithm is employed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form. At the end of the statistical timing, the sensitivity of all timing quantities to each of the sources of variation is available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature, which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in computer time, the probability of each edge or node of the timing graph being critical is computed. Numerical results are presented on industrial application-specified integrated circuit (ASIC) chips with over two million logic gates, and statistical timing results are compared to exhaustive corner analysis on a chip design whose hardware showed early mode timing violations Chandramouli Visweswariah, Kerim Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, Jeff Piaget, Natesan Venkateswaran, Jeffrey G. Hemmett	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	6
2003	Formal verification - prove it or pitch it abstract Despite a number of solid advances in simulation and verification techniques over the last twenty years, semiconductor chip designs continue to see large increases in the cost of verification - both in terms of human resources and time. Most of these increases are due to the growing size and complexity of the chip designs. Many of these designs are complete systems in their own right thus enlarging the scope of the verification problem. Formal verification has held out the most promise for reducing the magnitude of the verification task. Indeed, most major microprocessor teams - at IBM, Intel and Motorola - have routinely hosted formal verification experts since the early '90s. ASIC vendors and their tool providers have been closely following these developments into a number of initiatives and new startup companies driven by that very promise of formal verification. Despite these developments, simulation continues to be the final source of signoff - if not confidence - in chip tapeouts. Why is this so? Formal verification is an important technology to be left at the margins of the validation task. Will formal verification eliminate or limit unit level verification and provide the necessary glue for a realistic validation flow? Will the testbenches be replaced by constraints and assertions? Can validation effort be reused? This panel will explore the issues related to building practical validation flows, and the technologies that the designer community can realistically look forward to materializing in their lifetimes. Rajesh K. Gupta 0001, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Carl Pixley, John O'Leary, Fabio Somenzi	DAC	5
2002	Blue Gene/L, a System-On-A-Chip abstract Summary form only given. Large powerful networks coupled to state-of-the-art processors have traditionally dominated supercomputing. As technology advances, this approach is likely to be challenged by a more cost-effective System-On-A-Chip approach, with higher levels of system integration. The scalability of applications to architectures with tens to hundreds of thousands of processors is critical to the success of this approach. Significant progress has been made in mapping numerous compute-intensive applications, many of them grand challenges, to parallel architectures. Applications hoping to efficiently execute on future supercomputers of any architecture must be coded in a manner consistent with an enormous degree of parallelism. The BG/L program is developing a peak nominal 180 TFLOPS (360 TFLOPS for some applications) supercomputer to serve a broad range of science applications. BG/L generalizes QCDOC, the first System-On-A-Chip supercomputer that is expected in 2003. BG/L consists of 65,536 nodes, and contains five integrated networks: a 3D torus, a combining tree, a Gb Ethernet network, barrier/global interrupt network and JTAG. George S. Almási, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, Alina Deutsch, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, Blake G. Fitch, Joseph Gagliano, Alan Gara, Robert S. Germain, Mark Giampapa, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, T. Jamal-Eddine, Gerard V. Kopcsay, Alphonso P. Lanzetta, Derek Lieber, M. Lu, Mark P. Mendell, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Rick A. Rand, Richard D. Regan, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, Sarabjeet Singh, Peilin Song, Burkhard D. Steinmacher-Burow, Karin Strauss, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, J. Brown, Thomas A. Liebsch, A. Schram, G. Ulsh	CLUSTER	2
2002	An overview of the BlueGene/L Supercomputer abstract This paper gives an overview of the BlueGene/L Supercomputer. This is a jointly funded research partnership between IBM and the Lawrence Livermore National Laboratory as part of the United States Department of Energy ASCI Advanced Architecture Research Program. Application performance and scaling studies have recently been initiated with partners at a number of academic and government institutions,including the San Diego Supercomputer Center and the California Institute of Technology. This massively parallel system of 65,536 nodes is based on a new architecture that exploits system-on-a-chip technology to deliver target peak processing power of 360 teraFLOPS (trillion floating-point operations per second). The machine is scheduled to be operational in the 2004-2005 time frame, at price/performance and power consumption/performance targets unobtainable with conventional architectures. Narasimha R. Adiga, Gheorghe Almási 0001, George S. Almási, Yariv Aridor, Rajkishore Barik, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Waiman Chan, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, K. M. Desai, Alina Deutsch, Tamar Domany, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, C. Christopher Erway, J. Esch, Blake G. Fitch, Joseph Gagliano, Alan Gara, Rahul Garg 0001, Robert S. Germain, Mark Giampapa, Balaji Gopalsamy, John A. Gunnels, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, R. D. Jackson, T. Jamal-Eddine, Gerard V. Kopcsay, Elie Krevat, Manish P. Kurhekar, Alphonso P. Lanzetta, Derek Lieber, L. K. Liu, M. Lu, Mark P. Mendell, A. Misra, Yosef Moatti, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Adam J. Oliner, Vinayaka Pandit, R. B. Pudota, Rick A. Rand, Richard D. Regan, Bradley Rubin, Albert E. Ruehli, Silvius Vasile Rus, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, M. Sharma, Edi Shmueli, Sarabjeet Singh, Peilin Song, Vijay Srinivasan, Burkhard D. Steinmacher-Burow, Karin Strauss, Christopher W. Surovic, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Arun R. Umamaheshwaran, P. Verma, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, W. Barrett, C. Engel, B. Drehmel, B. Hilgart, D. Hill, F. Kasemkhani, David J. Krolak, Chun-Tao Li 0001, Thomas A. Liebsch, James A. Marcella, A. Muff, A. Okomo, M. Rouse, A. Schram, M. Tubbs, G. Ulsh, Charles D. Wait, J. Wittrup, Myung Bae, Kenneth A. Dockser, Lynn Kissel, Mark K. Seager, Jeffrey S. Vetter, K. Yates	SC	6
1997	Design Methodology for the High-Performance G4 S/390 abstract This paper describes the methodology employed in the design of the G4 S/390 microprocessor. Issues of verifying design metrics of power, noise, timing, and functional correctness are discussed within the context of a performance-driven transistor-level custom design approach. Semi-automated techniques to encourage designer productivity consistent with the objectives of a high-frequency deep submicron design point are presented as are the practical issues associated with managing the complexity of an 8 million transistor design. Kenneth L. Shepard, Sean M. Carey, Daniel K. Beece, Robert F. Hatch, Gregory A. Northrop	ICCD	3
1988	The IBM Engineering Verification Engine Daniel K. Beece, George Deibert, Georgina Papp, Frank Villante	DAC	1
1988	SLS-a fast switch-level simulator [for MOS] abstract SLS, a large-capacity, high-performance switch-level simulator developed to run on an IBM System/370 architecture is described. SLS uses a model which closely reflects the behavior of MOS circuits. The high performance is the result of mixing a compiled model with the more traditional approach of event-driven simulation control, together with very efficient algorithms for evaluating the steady-state response of the circuit. SLS is used for design verification/checking applications and for estimating fault coverage.> Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2
1986	SLS - a fast switch level simulator for verification and fault coverage analysis abstract We describe SLS, a large capacity, high performance switch level simulator, developed to run on an IBM System/370 architecture, that uses a model which closely reflects the behavior of MOS circuits. This performance is the result of mixing a compiled model with the more traditional approach of event-driven simulation control, together with very efficient algorithms for evaluating the steady state response of the circuit. SLS is used for design verification/checking applications and for estimating fault coverage. Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman	DAC	2